Download Print this page
Microchip Technology MEC172 Series Layout Manual
Microchip Technology MEC172 Series Layout Manual

Microchip Technology MEC172 Series Layout Manual

Advertisement

Quick Links

PCB Layout Guide for MEC172x
Author:
Tom Rubino
Microchip Technology Inc.
INTRODUCTION
This application note provides information on design considerations for a printed circuit board (PCB) for the Microchip
MEC1721/MEC1723 device.
The design of the PCB requires care to provide good supply and ground paths; in addition, other design issues are
addressed in this document.
The functional blocks in the MEC1721/MEC1723 have different requirements for routing and external connections,
which are also outlined in this application note.
Please see
References
for device-level information such as V
for the 176-Pin WFBGA.
This document includes the following topics:
Section 1.0, "General Layout Considerations," on page 2
Section 2.0, "Miscellaneous Considerations," on page 9
Section 3.0, "JTAG Design and Layout Guide," on page 24
Section 4.0, "Boards bring-up debug tips," on page 29
Audience
This document is written for a reader that is familiar with hardware design. The goal of this application note is to provide
information about sensitive areas of the MEC1721/MEC1723 PCB layout.
References
The following documents should be referenced when using this application note. Please contact your Microchip repre-
sentative for availability.
• Microchip MEC1721/MEC1723 Data Sheet
• Microchip MEC1721/MEC1723 EVBs, ASSY. 6906A
• PCI Local Bus Specification (see www.pcisig.com)
2
• I
C-bus specification and user manual, Rev. 6 - 4 April, 2014 or later (see
UM10204.pdf)
• Intel, Enhanced Serial Peripheral Interface (eSPI) Specification (for Client Platform)
• Microchip "eSPI Controller" Specification
Package Information
The MEC1721/MEC1723 device is currently available in the following packages:
• MEC1721/MEC1723 for 176-pin, WFBGA/LJ
• MEC1721/MEC1723 for 144-pin, WFBGA/SZ
 2021 Microchip Technology Inc. and its subsidiaries
AN3759
power planes, and mechanical package information
CC1
www.nxp.com/documents/user_manual/
DS00003759B-page 1

Advertisement

loading
Need help?

Need help?

Do you have a question about the MEC172 Series and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Summary of Contents for Microchip Technology MEC172 Series

  • Page 1 • Intel, Enhanced Serial Peripheral Interface (eSPI) Specification (for Client Platform) • Microchip “eSPI Controller” Specification Package Information The MEC1721/MEC1723 device is currently available in the following packages: • MEC1721/MEC1723 for 176-pin, WFBGA/LJ • MEC1721/MEC1723 for 144-pin, WFBGA/SZ  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 1...
  • Page 2: Decoupling Capacitors

    Schematics and Bill of Materials. 1.1.1 MEC1721/MEC1723 WFBGA CAPACITORS • Figure 1-1 shows decoupling for the MEC1721/MEC1723 176-pin WFBGA package. Note: The capacitors can use any typical 16V 10% ceramic.  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 2...
  • Page 3 C16 = 0.1uF on VREF_ADC C13 = 0.1uF on VTR_PLL C7 = 1uF Low ESR +/-20% <100 mOhm on CAP (X5R or X7R) Y1 = 12.5pF load crystal, C5/C6 are 22pF XTAL1, XTAL2  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 3...
  • Page 4 C14 = 0.1uF on VTR_REG C15 = 0.1uF on VTR_ANALOG C16 = 0.1uF on VREF_ADC C13 = 0.1uF on VTR_PLL C7 = 1uF Low ESR +/-20% <100 mOhm on CAP (X5R or X7R)  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 4...
  • Page 5 For Single ended XTAL configuration, external clock should be connected to XTAL2 pin and XTAL1 pin should be grounded. If the 32KHz source will never be the crystal oscillator, then the XTAL1 and XTAL2 pins should be grounded.  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 5...
  • Page 6 • Vias – next generation PCB technology for tighter pitches • Eliminate through-hole vias • Increase routing density & enhance electrical performance • Decrease routing layers • Provide fan-out solutions for multiple layers (stacked Vias)  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 6...
  • Page 7 AN3759 FIGURE 1-4: LAND PATTERN DIMENSIONS, 176-WFBGA/LJ, 0.65MM BALL PITCH  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 7...
  • Page 8 AN3759 FIGURE 1-5: LAND PATTERN DIMENSIONS, 144-WFBGA/SZ  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 8...
  • Page 9: Strapping Options

    0=Use the eSPI Flash Channel for Boot Note 1 GPIO126 UART_BSTRAP Crisis Recovery over UART VTR1 1=Normal Operation 0=Use UART interface for Crisis recovery Note 5 GPIO227 PWRGD_STRAP Power Good VTR1  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 9...
  • Page 10: Battery Circuit

    HOST RESET SELECT The platform reset signal that will be used to assert nSIO_RSET is determined by the POWER RESET CONTROL Reg- ister (40080114h) Bit 8 = 0 - eSPI_PLTRST# pin.  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 10...
  • Page 11 EOS is defined as damage to the part caused by the application of voltages (to any pin) beyond the power supply rails, usually forward biasing internal protection diodes and resulting in high levels of  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 11...
  • Page 12 Pin Function Signal Description Name Function Name Pin Number SPICLK SHD_CLK Shared SPI Clock PVT_CLK Private SPI Clock SPI_CS# SHD_CS0# P5/P8 Shared SPI Chip Selects PVT_CS# Private SPI Chip Selects  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 12...
  • Page 13 2-4. The pull-down both holds RSMRST# low glitch-free during the power-on sequence, as required by the core logic, and informs the Boot ROM in the MEC1721/ MEC1723 to use the eSPI Flash Channel.  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 13...
  • Page 14 Section 2.7.4, "Non-shared SPI Flash Interface" describes implementing the SPI Flash Inter- face using private signals (for example, PVT_CLK). Section 2.7.4, "Non-shared SPI Flash Interface," on page 16 for further details of this setup.  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 14...
  • Page 15 Pull-high resistor to +3.3V for SPI CS connections; between the 2.2K ohm MEC1721/MEC1723 or Host/PCH and the SPI flash device. This pull-high must connect to the same power rail of the SPI flash.  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 15...
  • Page 16 0.1-inch to 0.5-inch nation resistors. The PCB trace between terminating resistors on the IO lines. 1-inch to 10-inch The PCB trace from MEC1721/MEC1723 or R1 resistor to SPI flash. 1-inch to 10-inch  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 16...
  • Page 17 MEC1721/MEC1723 TOPOLOGY FOR NON-SHARED DUA: SPI FLASH DEVICE MEC172x +3.3V Flash 1 0.5" 5" 5" 0.5" SHD_IO0 SHD_IO1 SHD_IO2 SHD_IO3 SHD_SCLK +3.3V +3.3V SHD_CS0# 5" SHD_CS1# Flash 2 0.5" +3.3V +3.3V  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 17...
  • Page 18 • Within the Intel PCH, a Schmitt trigger input is assumed on the IO data lines. • The output drivers for the SPI flash chip select pins should be programmed as open-drain using the GPIO Pin Control registers.  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 18...
  • Page 19 16V 10% ceramic. Unused VCI pins should be pulled up to VBAT via a 100K resistor. Please refer to the MEC1721/MEC1723 EVB Schematics and Bill of Materials. FIGURE 2-8: VBAT-POWERED CONTROL INPUT CIRCUIT  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 19...
  • Page 20 Transistors that are suitable for use are MMBT3904 or an equivalent. Ter- mination resistor values for use can be from 510 ohm to 1K ohm, see Figure • Table 2-6 for generated tem- perature values for selected resistors.  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 20...
  • Page 21 The Guardian will perform no calculations to translate the VSET voltage to an equivalent thermistor voltage. In addition, high and low limit comparisons are not changed so you should set these limits to the appropriate values.  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 21...
  • Page 22 PWM11/PROCHOT has an output only, but with polarity inversed to use a 2n7002 FET. It optionally accepts a PRO- CHOT input on the SB-TSI_CLK pin if an input is needed. FIGURE 2-11: PROCHOT IMPLEMENTATION  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 22...
  • Page 23 • Wait for the Prime Rails to come up by holding the EC in reset by the RESET_IN# pin. The example circuitry is shown in the figure below. 3.3V MEC172x Pull‐up Prime Rails  Power Good RESET_IN# OR Gate EC Reset Pull‐down Pull‐ down  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 23...
  • Page 24 The JTAG cable senses the voltage level on this line and drives the JTAG logic levels to the same voltage level from the target system. Test Data In Test Mode Select Test Clock  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 24...
  • Page 25 JTAG Cable Connection The motherboard VTR is always 3.3V. SWDCLK Use on JTAG_CLK pin if selected. Use on JTAG_TDO pin if selected. SWDIO Use on JTAG_TMS pin if selected. Motherboard ground connect  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 25...
  • Page 26 ARM Embedded Trace Macro Data 0 TRACEDAT1 ARM Embedded Trace Macro Data 1 TRACEDAT2 ARM Embedded Trace Macro Data 2 TRACEDAT3 ARM Embedded Trace Macro Data 3 TRACECLK ARM Embedded Trace Macro Data Clock  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 26...
  • Page 27: Jtag Reset

    • Production Mode with JTAG Port Enable: - Add a jumper to hold the JTAG_RST# line low during power up, then remove the jumper in order to ensure that it meets the 5.00 msec timing requirement.  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 27...
  • Page 28 The RC values need to be changed in order to compensate for the power supply time to ensure a 5.00 msec reset pulse, measured from VTR = 3.3V to JTAG_RST# = 0.8V. FIGURE 3-4: VTR VS. JTAG RISING TIME  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 28...
  • Page 29 ICD4/PICKIT4 or 3rd party debugger to the device. - If an valid image is loaded and executed, the application firmware is required to enable the JTAG/SWD port by the DEBUG ENABLE Register.  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 29...
  • Page 30 TABLE A-1: REVISION HISTORY Revision Section/Figure/Entry Correction DS00003759B (09-20-21) Section 2.7, "SPI Flash Imple- IOx Pull-High recommendation added. mentation" Section 4.0, "Boards bring-up Section added. debug tips" DS00003759A (12-01-20) Document Release  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 30...
  • Page 31 Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
  • Page 32: Worldwide Sales And Service

    Tel: 46-31-704-60-40 Tel: 631-435-6000 Sweden - Stockholm San Jose, CA Tel: 46-8-5090-4654 Tel: 408-735-9110 UK - Wokingham Tel: 408-436-4270 Tel: 44-118-921-5800 Canada - Toronto Fax: 44-118-921-5820 Tel: 905-695-1980 Fax: 905-695-2078  2021 Microchip Technology Inc. and its subsidiaries DS00003759B-page 32 09/14/21...

This manual is also suitable for:

Mec1722Mec1723