Microchip Technology MEC172 Series Layout Manual page 12

AN3759
current flow. This typically induces open failures by damaging the metal inside the part. EOS is
typically a low voltage, high current situation.
Note 2-2 ESD is the applied reverse bias to the PN junction -- heat due to power dissipation melts the silicon
in the part. ESD is typically a high transient voltage spike with low current situation.
2.6 ADC Input Layout Requirements
• It is suggested that the Analog-Digital Converter (ADC) Source AVSS reference connects to the MEC1721/
MEC1723 AVSS via a low noise AVSS island, which is shown in
• It is suggested that a low pass filter, see
components below are a good starting point, the R should has value between 100 ohm to 1.1 kohm and the C
should has value between 100pF to 2500pF. The RC values are based on high frequency cut off desired for the
application, F = 1 / ( 2* RC ).
FIGURE 2-3: ADC INPUT LOW PASS FILTER
• It is recommended that the ADC nets are spaced at least 20 mils from any high speed switching signals to prevent
cross talk that could add noise.
2.7 SPI Flash Implementation
The MEC1721/MEC1723 SPI flash interface enables the host and embedded controller (EC) access to an external SPI
flash device. The MEC1721/MEC1723 Data Sheet and Boot ROM Application Note have more details on detail infor-
mation (see References on page
ture.
Note: The SPI Flash Interface of MEC1721/MEC1723 can be selected either 3.3V or 1.8V. The SHD SPI inter-
face is on VTR2 power rail, and PVT SPI interface is on VTR1 power rail.
The standard set of SPI flash signals are designated with "SHD_" for shared connections, for example, SHD_CLK; for
details, see Section 2.7.3, "Shared SPI Flash
to another SPI flash device as private, protected data; these signals are designated with "PVT_," for example, PVT_-
CLK; for details, see Section 2.7.4, "Non-shared SPI Flash
as a general SPI interface labeled as "SPI_," for example, SPI_CLK.
TABLE 2-2: SPI INTERFACE SIGNALS
Generic Pin Signal
Name
SPICLK SHD_CLK
PVT_CLK
SPI_CS# SHD_CS0#
PVT_CS#
DS00003759B-page 12
Figure 2-3, be used on each ADC input of MEC1721/MEC1723. Filter
Source
R = 100 ohm to 1.1 kohm
Analog
Voltage
C = 100 pF to 2500 pF
1). This section describes specific PCB layout design considerations to setup this fea-
Interface". MEC1721/MEC1723 has an added set of signals for connection
Interface". The MEC1721/MEC1723 has a third SPI interface
Pin Signal MEC1721/MEC1723
Function Name
N7
E12
P5/P8
G12
Figure 1-3.
ADC_IN
AVSS
Pin Function Signal Description
Pin Number
Shared SPI Clock
Private SPI Clock
Shared SPI Chip Selects
Private SPI Chip Selects
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