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Cypress Semiconductor Perform CY14B102N Manual

8 mbit (1024k x 8/512k x 16) nvsram
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Features
■
20 ns, 25 ns, and 45 ns access times
■
Internally organized as 1024K x 8 (CY14E108L) or 512K x 16
(CY14E108N)
■
Hands off automatic STORE on power down with only a small
capacitor
®
■
STORE to QuantumTrap
nonvolatile elements initiated by
software, device pin, or AutoStore
■
RECALL to SRAM initiated by software or power up
■
Infinite read, write, and recall cycles
■
200,000 STORE cycles to QuantumTrap
■
20 year data retention
■
Single 5V +10% operation
■
Commercial and industrial temperatures
■
48-pin FBGA, 44 and 54-pin TSOP II packages
■
Pb-free and RoHS compliance
Logic Block Diagram
Address
Note
1. Address A
- A
and Data DQ0 - DQ7 for x8 configuration, Address A
0
19
Cypress Semiconductor Corporation
Document Number: 001-45524 Rev. *A
ADVANCE
8 Mbit (1024K x 8/512K x 16) nvSRAM
®
on power down
V
V
CC
[1]
A
- A
0
19
CE
CY14E108L
OE
CY14E108N
WE
BHE
BLE
V
SS
- A
and Data DQ0 - DQ15 for x16 configuration.
0
18
•
198 Champion Court
CY14E108L, CY14E108N

Functional Description

The Cypress CY14E108L/CY14E108N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 1024K words of 8 bits each or 512K words of 16
bits each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world's most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
CAP
DQ0 - DQ7
HSB
,
•
San Jose
CA 95134-1709
[1]
•
408-943-2600
Revised June 24, 2008
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Summary of Contents for Cypress Semiconductor Perform CY14B102N

  • Page 1: Functional Description

    Features ■ 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 1024K x 8 (CY14E108L) or 512K x 16 (CY14E108N) ■ Hands off automatic STORE on power down with only a small capacitor ® ■ STORE to QuantumTrap nonvolatile elements initiated by ®...
  • Page 2 Pinouts 48-FBGA (x8) Top View (not to scale) 44 - TSOP II (x8) Top View (not to scale) Note 2. Address expansion for 16 Mbit. NC pin not connected to die. Document Number: 001-45524 Rev. *A ADVANCE Figure 1. Pin Diagram - 48 FBGA DQ10 DQ11 DQ12...

  • Page 3: Pin Definitions

    Pin Definitions Pin Name IO Type – A Input Address Inputs Used to Select One of the 1,048,576 bytes of the nvSRAM for x8 Configuration. – A Address Inputs Used to Select One of the 524, 288 bytes of the nvSRAM for x16 Configuration. DQ0 –...
  • Page 4 Device Operation The CY14E108L/CY14E108N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation).
  • Page 5 Software STORE Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14B108L/CY14B108N software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements.

  • Page 6: Data Protection

    Table 1. Mode Selection (continued) Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed: 1.

  • Page 7: Maximum Ratings

    Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ... –65°C to +150°C Ambient Temperature with Power Applied ... –55°C to +150°C Supply Voltage on V Relative to GND ...–0.5V to 7.0V Voltage Applied to Outputs in High-Z State...

  • Page 8: Thermal Resistance

    Capacitance In the following table, the capacitance parameters are listed Parameter Description Input Capacitance Output Capacitance Thermal Resistance In the following table, the thermal resistance parameters are listed Parameter Description Θ Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) and procedures for measuring thermal Θ...
  • Page 9 AC Switching Characteristics In the following table, the AC switching characteristics are listed. Parameters Cypress Parameters Parameters SRAM Read Cycle Chip Enable Access Time [10] Read Cycle Time [11] Address Access Time Output Enable to Data Valid Output Hold After Address Change [12] Chip Enable to Output Active LZCE...
  • Page 10 AutoStore and Power Up RECALL Parameters [14] Power Up RECALL Duration HRECALL [15] STORE Cycle Duration STORE Low Voltage Trigger Level SWITCH VCC Rise Time VCCRISE Software Controlled STORE and RECALL Cycle In the following table, the software controlled STORE/RECALL cycle parameters are listed. Parameters Description STORE/RECALL Initiation Cycle Time...
  • Page 11 Switching Waveforms (continued) Figure 6. SRAM Read Cycle #2: CE and OE Controlled ADDRESS BHE , BLE DQ (DATA OUT) STANDBY Figure 7. SRAM Write Cycle #1: WE Controlled ADDRESS BHE , BLE DATA IN DATA OUT PREVIOUS DATA Notes 22.
  • Page 12 Switching Waveforms (continued) Figure 8. SRAM Write Cycle #2: CE Controlled ADDRESS BHE , BLE DATA IN DATA OUT SWITCH VCCRISE AutoStore POWER-UP RECALL HRECALL Read & Write Inhibited Note 24. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V Document Number: 001-45524 Rev.
  • Page 13 Switching Waveforms (continued) Figure 10. CE Controlled Software STORE/RECALL Cycle Figure 11. OE Controlled Software STORE/RECALL Cycle ADDRESS # 1 ADDRESS DQ (DATA) DATA VALID Document Number: 001-45524 Rev. *A ADVANCE ADDRESS # 6 GHAX DATA VALID CY14E108L, CY14E108N [17] [17] STORE RECALL...
  • Page 14 Switching Waveforms (continued) Document Number: 001-45524 Rev. *A ADVANCE [20] Figure 12. Hardware STORE Cycle [18, 19] Figure 13. Soft Sequence Processing CY14E108L, CY14E108N Page 14 of 20 [+] Feedback...

  • Page 15: Ordering Information

    Ordering Information Speed Ordering Code (ns) CY14E108L-ZS20XCT CY14E108L-ZS20XIT CY14E108L-ZS20XI CY14E108L-BA20XCT CY14E108L-BA20XIT CY14E108L-BA20XI CY14E108L-ZSP20XCT CY14E108L-ZSP20XIT CY14E108L-ZSP20XI CY14E108N-BA20XCT CY14E108N-BA20XIT CY14E108N-BA20XI CY14E108N-ZSP20XCT CY14E108N-ZSP20XIT CY14E108N-ZSP20XI CY14E108L-ZS25XCT CY14E108L-ZS25XIT CY14E108L-ZS25XI CY14E108L-BA25XIT CY14E108L-BA25XI CY14E108N-BA25XCT CY14E108L-ZSP25XCT CY14E108L-ZSP25XIT CY14E108L-ZSP25XI CY14E108N-BA25XCT CY14E108N-BA25XIT CY14E108N-BA25XI CY14E108N-ZSP25XCT CY14E108N-ZSP25XIT CY14E108N-ZSP25XI Document Number: 001-45524 Rev. *A ADVANCE Package Package Type...

  • Page 16: Part Numbering Nomenclature

    Ordering Information (continued) Speed Ordering Code (ns) CY14E108L-ZS45XCT CY14E108L-ZS45XIT CY14E108L-ZS45XI CY14E108L-BA45XCT CY14E108L-BA45XIT CY14E108L-BA45XI CY14E108L-ZSP45XCT CY14E108L-ZSP45XIT CY14E108L-ZSP45XI CY14E108N-BA45XCT CY14E108N-BA45XIT CY14E108N-BA45XI CY14E108N-ZSP45XCT CY14E108N-ZSP45XIT CY14E108N-ZSP45XI All parts are Pb-free. The above table contains Advance information. Please contact your local Cypress sales representative for availability of these parts. Part Numbering Nomenclature CY 14 E 108 L - ZS P 20 X C T Pb-Free...

  • Page 17: Package Diagrams

    Package Diagrams TOP VIEW 0.400(0.016) 0.800 BSC 0.300 (0.012) (0.0315) 18.517 (0.729) 18.313 (0.721) Document Number: 001-45524 Rev. *A ADVANCE Figure 14. 44-Pin TSOP II (51-85087) PIN 1 I.D. BASE PLANE 0°-5° 0.10 (.004) 0.597 (0.0235) 0.406 (0.0160) SEATING PLANE CY14E108L, CY14E108N DIMENSION IN MM (INCH) MIN.
  • Page 18 Package Diagrams (continued) Figure 15. 48-ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128) TOP VIEW A1 CORNER 6.00±0.10 SEATING PLANE Document Number: 001-45524 Rev. *A ADVANCE CY14E108L, CY14E108N 0.15(4X) BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) 1.875...
  • Page 19 ADVANCE CY14E108L, CY14E108N Package Diagrams (continued) Figure 16. 54-Pin TSOP II (51-85160) 51-85160-** Document Number: 001-45524 Rev. *A Page 19 of 20 [+] Feedback...
  • Page 20 Document History Page Document Title: CY14E108L/CY14E108N 8 Mbit (1024K x 8/512K x 16) nvSRAM Document Number: 001- 45524 Submission REV. ECN NO. Date 2428826 See ECN 2520023 06/23/08 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

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