Features
Powerful Harvard Architecture Processor
■
M8C Processor Speeds to 24 MHz
❐
Low power at high speed
❐
2.4V to 5.25V Operating Voltage
❐
Operating Voltages Down to 1.0V using On-Chip Switch
❐
Mode Pump (SMP)
Industrial Temperature Range: -40°C to +85°C
❐
Advanced Peripherals (PSoC
■
4 Analog Type "E" PSoC Blocks provide:
❐
• 2 Comparators with DAC Refs
• Single or Dual 8-Bit 28 Channel ADC
4 Digital PSoC Blocks provide:
❐
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART, SPI™ Master or Slave
• Connectable to All GPIO Pins
Complex Peripherals by Combining Blocks
❐
Flexible On-Chip Memory
■
8K Flash Program Storage 50,000 Erase/Write Cycles
❐
512 Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
❐
Complete Development Tools
■
Free Development Software
❐
(PSoC Designer™)
Full-Featured, In-Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Trace Memory
❐
Precision, Programmable Clocking
■
Internal ±2.5% 24/48 MHz Oscillator
❐
Internal Oscillator for Watchdog and Sleep
❐
Programmable Pin Configurations
■
25 mA Sink, 10 mA Drive on All GPIO
❐
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
❐
Modes on All GPIO
Up to 8 Analog Inputs on GPIO
❐
Configurable Interrupt on All GPIO
❐
Cypress Semiconductor Corporation
Document Number: 38-12025 Rev. *O
PSoC
®
Blocks)
•
198 Champion Court
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
®
Programmable System-on-Chip™
Versatile Analog Mux
■
Common Internal Analog Bus
❐
Simultaneous Connection of IO Combinations
❐
Capacitive Sensing Application Capability
❐
Additional System Resources
■
2
I
C Master, Slave and Multi-Master to 400 kHz
❐
Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
❐
Logic Block Diagram
,
•
San Jose
CA 95134-1709
•
408-943-2600
Revised April 06, 2009
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