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MoBL-USB™ TX2 Features
UTMI-compliant and USB 2.0 certified for device operation
■
Operates in both USB 2.0 High Speed (HS), 480 Mbits/second,
■
and Full Speed (FS), 12 Mbits/second
Optimized for Seamless Interface with Intel
■
cations Processors
Tri-state Mode enables sharing of UTMI Bus with other devices
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Serial-to-Parallel and Parallel-to-Serial Conversions
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8-bit Unidirectional, 8-bit Bidirectional, or 16-bit Bidirectional
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External Data Interface
Synchronous Field and EOP Detection on Receive Packets
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Synchronous Field and EOP Generation on Transmit Packets
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Data and Clock Recovery from the USB Serial Stream
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Bit stuffing and unstuffing; Bit Stuff Error Detection
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Staging Register to manage Data Rate variation due to Bit
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stuffing and unstuffing
16-bit 30 MHz and 8-bit 60 MHz Parallel Interface
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Ability to switch between FS and HS terminations and signaling
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Supports detection of USB Reset, Suspend, and Resume
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Supports HS identification and detection as defined by the USB
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2.0 Specification
Logic Block Diagram
Cypress Semiconductor Corporation
Document #: 38-08052 Rev. *G
MoBL-USB™ TX2 USB 2.0 UTMI
Supports transmission of Resume Signaling
■
3.3V Operation
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Two package options: 56-pin QFN and 56-pin VFBGA
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All required terminations, including 1.5 Kohm pull up on
■
DPLUS, are internal to chip
®
Monahans Appli-
Supports USB 2.0 Test Modes
■
The Cypress MoBL-USB TX2 is a Universal Serial Bus (USB)
specification revision 2.0 transceiver, serial and deserializer, to a
parallel interface of either 16 bits at 30 MHz or eight bits at 60
MHz. The MoBL-USB TX2 provides a high speed physical layer
interface that operates at the maximum allowable USB 2.0
bandwidth. This enables the system designer to keep the
complex high speed analog USB components external to the
digital ASIC. This decreases development time and associated
risk. A standard USB 2.0-certified interface is provided and is
compliant with Transceiver Macrocell Interface (UTMI) specifi-
cation version 1.05 dated 3/29/2001.
This product is also optimized to seamlessly interface with
Monahans -P & -L applications processors. It has been charac-
terized by Intel and is recommended as the USB 2.0 UTMI trans-
ceiver of choice for its Monahans processors. It is also capable
of tri-stating the UTMI bus, while suspended, to enable the bus
to be shared with other devices.
Two packages are defined for the family: 56-pin QFN and 56-pin
VFBGA.
The functional block diagram follows.
•
198 Champion Court
,
•
San Jose
CA 95134-1709
CY7C68000A
Transceiver
Tri_state
•
408-943-2600
Revised October 5, 2008
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Summary of Contents for Cypress Semiconductor MoBL-USB CY7C68000A
- Page 1 MoBL-USB™ TX2 Features UTMI-compliant and USB 2.0 certified for device operation ■ Operates in both USB 2.0 High Speed (HS), 480 Mbits/second, ■ and Full Speed (FS), 12 Mbits/second Optimized for Seamless Interface with Intel ■ cations Processors Tri-state Mode enables sharing of UTMI Bus with other devices ■...
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Page 2: Functional Overview
Applications Mobile Applications Smart Phones ■ PDA Phones ■ Gaming Phones ■ MP3 players ■ Portable Media Players (PMP) ■ GPS Tracking Devices ■ Consumer Applications Cameras ■ Scanners ■ DSL Modems ■ Memory Card Readers ■ Non-Consumer Applications Networking ■... - Page 3 Operational Modes The operational modes are controlled by the OpMode signals. The OpMode signals are capable of inhibiting normal operation of the transceiver and evoking special test modes. These modes take effect immediately and take precedence over any pending data operations. The transmission data rate when in OpMode depends on the state of the XcvrSelect input.
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Page 4: Pin Configurations
Pin Configurations The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin VFBGA packages. The packages offered use either an 8-bit (60 MHz) or 16-bit (30 MHz) bus interface. Figure 1. CY7C68000A 56-pin QFN Pin Assignment TXReady Suspend Reset... - Page 5 Figure 2. CY7C68000A 56-pin VFBGA Pin Assignment Document #: 38-08052 Rev. *G CY7C68000A Page 5 of 15 [+] Feedback...
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Page 6: Pin Descriptions
Pin Descriptions Table 1. Pin Descriptions QFN VFBGA Name Type AVCC Power AVCC Power AGND Power AGND Power DPLUS I/O/Z DMINUS I/O/Z Output Reset Input XcvrSelect Input TermSelect Input Suspend Input Note 1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled up or down to ensure signals at power-up and in standby. - Page 7 Table 1. Pin Descriptions (continued) QFN VFBGA Name Type Tri_state Input LineState1 Output LineState0 Output OpMode1 Input OpMode0 Input TXValid Input TXReady Output Document #: 38-08052 Rev. *G Default Description Tri-state Mode Enable Places the CY7C68000A into Tri-state mode which tri-states all outputs and IOs. Tri-state Mode can only be enabled while suspended.
- Page 8 Table 1. Pin Descriptions (continued) QFN VFBGA Name Type RXValid Output RXActive Output RXError Output ValidH DataBus16_8 Input XTALIN Input XTALOUT Output Uni_Bidi Input Power Power Power Power Power Ground Ground Ground Ground Ground Reserved INPUT Reserved INPUT Reserved INPUT Reserved INPUT Document #: 38-08052 Rev.
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Page 9: Absolute Maximum Ratings
Absolute Maximum Ratings Storage Temperature ... –65°C to +150°C Ambient Temperature with Power Supplied ... 0°C to +70°C Supply Voltage to Ground Potential ...–0.5V to +4.0V DC Input Voltage to Any Input Pin ... 5.25 V DC Voltage Applied to Outputs in High-Z State ... -
Page 10: Ac Electrical Characteristics
AC Electrical Characteristics USB 2.0 Transceiver USB 2.0-compliant in FS and HS modes. Timing Diagram HS/FS Interface Timing - 60 MHz TCSU_MIN Control_In TDSU_MIN DataIn Control_Out DataOut Table 3. 60 MHz Interface Timing Constraints Parameters Parameter Description Minimum setup time for TXValid CSU_MIN Minimum hold time for TXValid CH_MIN... - Page 11 HS/FS Interface Timing - 30 MHz Figure 4. 30 MHz Timing Interface Timing Constraints TCSU_MIN Control_In TDSU_MIN DataIn Control_Out TVSU_MIN DataOut Table 4. 30 MHz Timing Interface Timing Constraints Parameters Parameter Description Minimum setup time for TXValid CSU_MIN Minimum hold time for TXValid CH_MIN Minimum setup time for Data (Transmit direction) DSU_MIN...
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Page 12: Ordering Information
Ordering Information Ordering Code CY7C68000A-56LFXC CY7C68000A-56BAXC CY3683 Package Diagrams The MoBL-USB TX2 is available in two packages: 56-pin QFN ■ 56-pin VFBGA ■ Figure 6. 56-Pin Quad Flatpack No Lead Package 8 x 8 mm (Sawn Version) LS56B Document #: 38-08052 Rev. *G Package Type 56 QFN 56 VFBGA... -
Page 13: Pcb Layout Recommendations
Package Diagrams (continued) Figure 7. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 TOP VIEW PIN A1 CORNER 5.00±0.10 SIDE VIEW SEATING PLANE PCB Layout Recommendations Follow these recommendations to ensure reliable, high-perfor- mance operation A four-layer impedance controlled board is required to maintain ■... - Page 14 Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board.
- Page 15 Document History Page Document Title: CY7C68000A MoBL-USB™ TX2 USB 2.0 UTMI Transceiver Document Number: 38-08052 Orig. of Submission REV. ECN NO. Change 285592 See ECN 427959 See ECN 470121 See ECN 476107 See ECN 491668 See ECN 498415 See ECN 567869 See ECN 2587010...
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