Cypress Semiconductor MoBL CY62146ESL Specification Sheet

Features
■ Very high speed: 45 ns
■ Wide voltage range: 2.2V–3.6V and 4.5V–5.5V
■
Ultra low standby power
Typical Standby current: 1 μA
❐
Maximum Standby current: 7 μA
❐
■
Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Available in Pb-free 44-pin TSOP II package

Functional Description

The CY62146ESL is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
Logic Block Diagram
Cypress Semiconductor Corporation
Document #: 001-43142 Rev. **
®
) in portable
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
256K x 16
6
A
5
A RAM Array
4
A
3
A
2
A
1
A
0
COLUMN DECODER
• 198 Champion Court
CY62146ESL MoBL
4-Mbit (256K x 16) Static RAM
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (IO
IO ) are placed in a high impedance state when:
15
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO through IO
0
specified on the address pins (A
Enable (BHE) is LOW, then data from IO pins (IO
is written into the location specified on the address pins (A
through A ).
17
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO
Byte High Enable (BHE) is LOW, then data from memory
appears on IO to IO . See the
8 15
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System
IO –IO
0
IO –IO
8
,
• San Jose CA 95134-1709
through
0
) is written into the location
7
through A ). If Byte High
0 17
through IO
8
to IO
0
"Truth Table" on page 10 for a
Guidelines.
7
15
BHE
WE
CE
OE
BLE
• 408-943-2600
Revised January 04, 2008
®
)
15
0
. If
7
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