Cypress Semiconductor CY8C24123 Specification Sheet
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Cypress Semiconductor CY8C24123 Specification Sheet

Psoc programmable system-on-chip
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Features
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds to 24 MHz
❐
8x8 Multiply, 32-Bit Accumulate
❐
Low Power at High Speed
❐
3.0 to 5.25 V Operating Voltage
❐
Operating Voltages Down to 1.0V Using On-Chip Switch
Mode Pump (SMP)
❐
Industrial Temperature Range: -40°C to +85°C
■
Advanced Peripherals (PSoC Blocks)
❐
Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 8-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐
Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐
Complex Peripherals by Combining Blocks
■
Precision, Programmable Clocking
❐
Internal ± 2.5% 24/48 MHz Oscillator
❐
High-Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐
Optional External Oscillator, up to 24 MHz
❐
Internal Oscillator for Watchdog and Sleep
■
Flexible On-Chip Memory
❐
4K Bytes Flash Program Storage 50,000 Erase/Write Cycles
❐
256 Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP™)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
■
Programmable Pin Configurations
❐
25 mA Sink on all GPIO
❐
Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐
Up to 10 Analog Inputs on GPIO
❐
Two 30 mA Analog Outputs on GPIO
❐
Configurable Interrupt on all GPIO
Cypress Semiconductor Corporation
Document Number: 38-12011 Rev. *G
®
PSoC
Programmable System-on-Chip™
■
Additional System Resources
❐
I
❐
Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
■
Complete Development Tools
❐
Free Development Software (PSoC Designer™)
❐
Full-Featured, In-Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Bytes Trace Memory
Logic Block Diagram
Digital
Clocks
•
198 Champion Court
CY8C24223, CY8C24423
2
C™ Slave, Master, and Multi-Master to 400 kHz
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
SROM
Flash 4K
256 Bytes
CPU Core (M8C)
Interrupt
Controller
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Digital
Block Array
(1 Rows,
(2 Columns,
4 Blocks)
6 Blocks)
POR and LVD
Multiply
2
Decimator
I
C
Accum.
System Resets
SYSTEM RESOURCES
,
•
San Jose
CA 95134-1709
CY8C24123
Analog
Port 2 Port 1 Port 0
Drivers
Global Analog Interconnect
Sleep and
Watchdog
Analog
Analog
Ref
Block
Array
Analog
Input
Muxing
Internal
Switch
Voltage
Mode
Ref.
Pump
•
408-943-2600
Revised December 11, 2008
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Summary of Contents for Cypress Semiconductor CY8C24123

  • Page 1 Block Array (1 Rows, 4 Blocks) Digital Multiply Clocks Accum. • 198 Champion Court • San Jose CY8C24123 CY8C24223, CY8C24423 Analog Port 2 Port 1 Port 0 Drivers Global Analog Interconnect SROM Flash 4K CPU Core (M8C) Sleep and Watchdog...

  • Page 2: Functional Overview

    Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are listed in the table PSoC Device Characteristics page 4. CY8C24123 Port 0 To Analog System DCB03 GOE[7:0]...

  • Page 3: Analog System

    P2[3] P2[1] Array Input Configuration ACI0[1:0] Block Array ACB00 ASC10 ASD20 Interface to RefHi Digital System RefLo AGND M8C Interface (Address Bus, Data Bus, Etc.) CY8C24123 P0[6] P0[4] P0[2] P0[0] P2[6] P2[4] P2[2] P2[0] ACI1[1:0] ACB01 ASD11 ASC21 Analog Reference...

  • Page 4: Getting Started

    To view the PSoC application notes, go to the http://www.cypress.com under the Design Resources list located in the center of the web page. Application notes are listed by date as default. CY8C24123 CY8C24223, CY8C24423 web site and select Application Notes Page 4 of 43...

  • Page 5: Development Tools

    The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with Device embedded libraries providing port and bus operations, standard Programmer keypad and display support, and extended math functionality. CY8C24123 CY8C24223, CY8C24423 dynamic reconfiguration. Dynamic Page 5 of 43...

  • Page 6: Hardware Tools

    “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. CY8C24123 Page 6 of 43 [+] Feedback...

  • Page 7: Document Conventions

    ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. CY8C24123 CY8C24223, CY8C24423 Description on page 11 lists all the abbreviations used to ‘b’...
  • Page 8 Power Supply voltage LEGEND: A = Analog, I = Input, and O = Output. Document Number: 38-12011 Rev. *G CY8C24223, CY8C24423 Figure 6. CY8C24123 8-Pin PSoC Device Description I2C SCL, XTALin, P1[1] Figure 7. CY8C24223 20-Pin PSoC Device Description AI, P0[7]...
  • Page 9 Description AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] AI, P2[3] AI, P2[1] I2C SCL, P1[7] I2C SDA, P1[5] I2C SCL, XTALin, P1[1] CY8C24123 CY8C24223, CY8C24423 P0[6], AI P0[4], AI P0[2], AI P2[7] P0[0], AI P2[5] P2[6], External VRef PDIP...
  • Page 10 Document Number: 38-12011 Rev. *G Figure 9. CY8C24423 32-Pin PSoC Device Description P2[7] P2[5] AI, P2[3] AI, P2[1] I2C SCL, P1[7] I2C SDA, P1[5] CY8C24123 CY8C24223, CY8C24423 P0[2], AI P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI (Top View) P2[0], AI...

  • Page 11: Register Reference

    “extended” address space or the “config- uration” registers. Note In the following register mapping tables, blank fields are Reserved and must not be accessed. CY8C24123 CY8C24223, CY8C24423 Page 11 of 43 [+] Feedback...
  • Page 12 ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 # Access is bit specific. CY8C24123 CY8C24223, CY8C24423 I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1...
  • Page 13 # Access is bit specific. ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 # Access is bit specific. CY8C24123 CY8C24223, CY8C24423 ACC_DR3 ACC_DR2 CPU_F CPU_SCR1 CPU_SCR0 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Page 13 of 43 [+] Feedback...
  • Page 14 Blank fields are Reserved and must not be accessed. Document Number: 38-12011 Rev. *G ASC21CR3 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDIOLT1 RDI0RO0 RDI0RO1 # Access is bit specific. CY8C24123 CY8C24223, CY8C24423 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP IMO_TR ILO_TR...

  • Page 15: Electrical Specifications

    Unit of Measure μW micro watts milli-ampere milli-second milli-volts nano ampere nanosecond nanovolts pico ampere pico farad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts CY8C24123 CY8C24223, CY8C24423 24 MHz Page 15 of 43 [+] Feedback...

  • Page 16: Absolute Maximum Ratings

    +100 The temperature rise from ambient to junction is package specific. See Thermal Impedances per Package on page 41. The user must limit the power consumption to comply with this requirement. CY8C24123 Notes Notes Page 16 of 43 [+] Feedback...

  • Page 17: Dc Electrical Characteristics

    – μA – μA – 1.275 1.325 CY8C24123 Notes Conditions are Vdd = 5.0V, 25 CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are Vdd = 3.3V, T...
  • Page 18 ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and – – – – 35.0 – – – – Vdd - 0.5 – CY8C24123 Notes Units Notes μV/ Gross tested to 1 μA. Package and pin dependent. Temp = 25 The common-mode input voltage range is measured through an analog output buffer.
  • Page 19 – Vdd - 0.5 – – – – – – – – μA – μA – μA – μA – 1200 1600 μA – 2400 3200 μA – 4600 6400 – – CY8C24123 Notes Page 19 of 43 [+] Feedback...
  • Page 20 – Vdd - 0.2 – – – – – – – – μA – μA – μA – μA – 1200 1600 μA – 2400 3200 μA – 4600 6400 – – CY8C24123 Notes Page 20 of 43 [+] Feedback...
  • Page 21 – – – – – – – – 0.5 x Vdd + 1.0 0.5 x Vdd + 1.0 – – – CY8C24123 Units μV/°C – – Vdd - 1.0 – – – – – – – 0.5 x Vdd - 1.3 –...
  • Page 22 – range) – – – – – Figure 11. Basic Switch Mode Pump Circuit Battery PSoC CY8C24123 CY8C24223, CY8C24423 Units Notes Average, neglecting ripple Average, neglecting ripple For implementation, which – includes 2 uH inductor, 1 uF cap, – and Schottky diode –...
  • Page 23 /2 - BG - 0.051 BG - 0.082 2 x BG - P2[6] - 0.084 P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 P2[4] - P2[6] - 0.057 CY8C24123 CY8C24223, CY8C24423 Units 1.30 1.326 Vdd/2 - 0.025 Vdd/2 + 0.003...
  • Page 24 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] - P2[6] - P2[4]- P2[6] + 0.048 0.022 CY8C24123 Units 1.326 Vdd/2 + 0.002 P2[4] + 0.009 BG + 0.015 1.6 x BG + 0.018 0.034 P2[4] + P2[6] + 0.057...
  • Page 25 – – – 2.863 2.963 3.070 3.920 4.393 4.550 4.632 4.718 2.963 3.033 3.185 4.110 4.550 4.632 4.719 4.900 CY8C24123 Units k Ω 12.24 – – Units 2.908 4.394 – 4.548 2.816 4.394 – 4.548 – – – 2.921 2.979 3.023...
  • Page 26 – Vss + 0.75 Vdd - 1.0 – 50,000 – 1,800,000 – – http://www.cypress.com under Application Notes for more information. CY8C24123 CY8C24223, CY8C24423 Units Notes – Driving internal pull down resistor. Driving internal pull down resistor. – – Erase/write cycles per block.

  • Page 27: Ac Electrical Characteristics

    “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for opera- period. Correct operation assumes a properly loaded 1 uW maximum osacc C ≤ T ≤ 85 CY8C24123 CY8C24223, CY8C24423 Units Notes Trimmed. Using factory trim values.
  • Page 28 Figure 16. 32 kHz Period Jitter (ECO) Timing Diagram 32K2 Document Number: 38-12011 Rev. *G Figure 12. PLL Lock Timing Diagram PLLSLEW PLLSLEWLOW Jitter24M1 Jitter32k CY8C24123 CY8C24223, CY8C24423 24 MHz 24 MHz 32 kHz Page 28 of 43 [+] Feedback...
  • Page 29 – – Figure 17. GPIO Timing Diagram TRiseF TFallF TRiseS TFallS CY8C24123 CY8C24223, CY8C24423 Units Notes Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90%...
  • Page 30 V/ μ s – 0.75 – – – – – nV/rt-Hz CY8C24123 Notes Specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. Specification maximums for...
  • Page 31 – opamp bias levels are – – – between low and high power levels. – – – – – nV/rt-Hz CY8C24123 Notes Page 31 of 43 [+] Feedback...
  • Page 32 – – – – – 16.4 – 49.2 CY8C24123 Notes 4.75V < Vdd < 5.25V 4.75V < Vdd < 5.25V 4.75V < Vdd < 5.25V 4.75V < Vdd < 5.25V 4.75V < Vdd < 5.25V Page 32 of 43 [+] Feedback...
  • Page 33 ≤ 85 ° C, respectively. Typical parameters apply to 5V and 3.3V at 25 ° C and , 3dB BW, 100 pF Load , 3dB BW, 100 pF Load , 3dB BW, 100 pF Load , 3dB BW, 100 pF Load CY8C24123 CY8C24223, CY8C24423 Units μ s –...
  • Page 34 ≤ 85 ° C, respectively. Typical parameters apply to 5V and 3.3V at 25 ° C and 20.6 20.6 41.7 41.7 ≤ 85 ° C, respectively. Typical parameters apply to 5V and 3.3V at 25 ° C and – – – CY8C24123 Units – 24.24 – – – – μ s –...
  • Page 35 ≤ 85 ° C, respectively. Typical parameters apply to 5V and 3.3V at 25 ° C and Standard Mode – ≥ 250 ns must then be met. This is automatically the SU;DAT HDSTAI2C SUSTOI2C SUSTAI2C CY8C24123 Fast Mode Units μ s – – μ s –...

  • Page 36: Packaging Information

    CY8C24123 CY8C24223, CY8C24423 Packaging Information This section presents the packaging specifications for the CY8C24x23 PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Figure 19. 8-Pin (300-Mil) PDIP 51-85075 *A Document Number: 38-12011 Rev. *G...
  • Page 37 CY8C24123 CY8C24223, CY8C24423 Figure 20. 8-Pin (150-Mil) SOIC 51-85066 *B 51-85066 *C Figure 21. 20-Pin (300-Mil) Molded DIP 51-85011-A 51-85011 *A Document Number: 38-12011 Rev. *G Page 37 of 43 [+] Feedback...
  • Page 38 CY8C24123 CY8C24223, CY8C24423 Figure 22. 20-Pin (210-Mil) SSOP 51-85077 *C Figure 23. 20-Pin (300-Mil) Molded SOIC 51-85024 *C Document Number: 38-12011 Rev. *G Page 38 of 43 [+] Feedback...
  • Page 39 CY8C24123 CY8C24223, CY8C24423 Figure 24. 28-Pin (300-Mil) Molded DIP 51-85014 *D Document Number: 38-12011 Rev. *G Page 39 of 43 [+] Feedback...
  • Page 40 CY8C24123 CY8C24223, CY8C24423 Figure 25. 28-Pin (210-Mil) SSOP 51-85079 *C Figure 26. 28-Pin (300-Mil) Molded SOIC 51-85026 *D Document Number: 38-12011 Rev. *G Page 40 of 43 [+] Feedback...

  • Page 41: Thermal Impedances

    Package 8 PDIP 8 SOIC 20 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 32 MLF CY8C24123 CY8C24223, CY8C24423 51-85188 *B Package Capacitance 2.8 pF 2.0 pF 3.0 pF 2.6 pF 2.5 pF 3.5 pF 2.8 pF 2.7 pF...

  • Page 42: Ordering Information

    The following table lists the CY8C24x23 PSoC Device family’s key package features and ordering codes. Table 38. CY8C24x23 PSoC Device Family Key Features and Ordering Information 8 Pin (300 Mil) DIP CY8C24123-24PI 8 Pin (150 Mil) SOIC CY8C24123-24SI 8 Pin (150 Mil) SOIC...
  • Page 43 New data sheet format and organization. Reference the PSoC Programmable System-on-Chip Technical Reference Manual for additional information. Title change. Changed title to “CY8C24123, CY8C24223, CY8C24423 PSoC® Programmable System-on-Chip™” Updated package diagrams 51-85188, 51-85024, 51-85014, and 51-85026. Added note on digital signaling in Added Die Sales information note to Updated data sheet template.

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