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Features
■
25 ns, 35 ns, and 45 ns access times
■
Pin compatible with STK17TA8
■
Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock (RTC)
❐
Low power, 350 nA RTC current
❐
Capacitor or battery backup for RTC
■
Watchdog timer
■
Clock alarm with programmable interrupts
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap™ initiated by software, device pin, or
on power down
■
RECALL to SRAM initiated by software or on power up
■
Infinite READ, WRITE, and RECALL cycles
Logic Block Diagram
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Cypress Semiconductor Corporation
Document Number: 001-06401 Rev. *I
1 Mbit (128K x 8) nvSRAM With Real Time Clock
■
High reliability
❐
Endurance to 200K cycles
❐
Data retention: 20 years at 55°C
■
Single 3V operation with tolerance of +20%, –10%
■
Commercial and industrial temperature
■
48-Pin SSOP package (ROHS compliant)
Functional Description
The Cypress CY14B101K combines a 1 Mbit nonvolatile static
RAM with a full featured real time clock in a monolithic integrated
circuit. The embedded nonvolatile elements incorporate
QuantumTrap technology producing the world's most reliable
nonvolatile memory. The SRAM is read and written an infinite
number of times, while independent, nonvolatile data resides in
the nonvolatile elements.
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable high accuracy oscillator.
The alarm function is programmable for one time alarm or
periodic seconds, minutes, hours, or days. There is also a
programmable watchdog timer for process control.
QuantumTrap
1024 x 1024
STORE
RECALL
STATIC RAM
ARRAY
1024 X 1024
COLUMN IO
COLUMN DEC
A
A
A
A
A
A
A
0
1
2
3
4
10
11
•
198 Champion Court
V
V
CC
CAP
V
RTCbat
POWER
CONTROL
V
RTCcap
STORE/
RECALL
HSB
CONTROL
SOFTWARE
A
DETECT
15
x
1
x
RTC
2
INT
-
A
A
MUX
16
OE
CE
WE
,
•
San Jose
CA 95134-1709
CY14B101K
-
A
0
0
•
408-943-2600
Revised February 24, 2009
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Summary of Contents for Cypress Semiconductor CY14B101K
-
Page 1: Functional Description
■ 48-Pin SSOP package (ROHS compliant) Functional Description The Cypress CY14B101K combines a 1 Mbit nonvolatile static RAM with a full featured real time clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. -
Page 2: Pin Configurations
Power Supply Battery Supplied Backup RTC Supply Voltage. (Left unconnected if V RTCbat Output Interrupt Output. Program to respond to the clock alarm, the watchdog timer, and the power monitor. Programmable to either active HIGH (push or pull) or LOW (open drain). Ground Ground for the Device. -
Page 3: Device Operation
During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The CY14B101K suppots infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations. - Page 4 CE or WE is detected. This protects against inadvertent writes during power up or brownout conditions. Noise Considerations The CY14B101K is a high speed memory and must have a high frequency bypass capacitor of approximately 0.1 µF connected between V and V as possible.
- Page 5 V chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY14B101K depends on the following items: ■ The duty cycle of chip enable ■...
- Page 6 1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle. 2. While there are 17 address lines on the CY14B101K, only the lower 16 lines are used to control software modes.
-
Page 7: Real Time Clock Operation
3V lithium; the CY14B101K only sources current from the battery when the primary power is removed. However, the battery is not recharged at any time by the CY14B101K. The battery capacity is chosen for total anticipated cumulative downtime required over the life of the system. - Page 8 32.768 kHz. Clock accuracy depends on the quality of the crystal and calibration. The crystal oscillators typically have an error of +20ppm to +35ppm. However, CY14B101K employs a calibration circuit that improves the accuracy to +1/–2 ppm at 25°C. This implies an error of +2.5 seconds to -5 seconds per month.
- Page 9 “AutoStore or Power Up RECALL” on page 19). Interrupts The CY14B101K has a Flags register, Interrupt register and Interrupt logic that can signal interrupt to the microcontroller. There are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. Each of these can be individually enabled to drive the INT pin by appropriate setting in the Interrupt register (0x1FFF6).
- Page 10 C1 = 0 (install cap footprint, but leave unloaded) C2 = 56 pF + 10% (do not vary from this value) and DQ in applications where undershoot exceeds -0.5V. Please see CY14B101K WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable...
- Page 11 WDT (000000) H/L (1) P/L (0) Alarm Day Alarm Hours Alarm Minutes Alarm, Seconds Centuries OSCF CAL (0) CY14B101K Function/Range Years: 00–99 Months: 01–12 Day of Month: 01–31 Day of Week: 01–07 Hours: 00–23 Minutes: 00–59 Seconds: 00–59 Calibration Values...
- Page 12 10s Day of Month Time Keeping - Day Time Keeping - Hours 10s Hours Time Keeping - Minutes 10s Minutes Time Keeping - Seconds 10s Seconds CY14B101K Years Months Day of Month Day of Week Hours Minutes Seconds Page 12 of 28...
- Page 13 Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base. Sign Calibration These five bits control the calibration of the clock. 0x1FFF7 Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit is cleared automatically after the watchdog timer is reset.
- Page 14 Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation. This indicates that RTC backup power failed and clock value is no longer valid. The user must reset this bit to 0 to clear this condition (Flag).
-
Page 15: Maximum Ratings
< V , CE or OE > V = –2 mA = 4 mA Between V pin and V , 5V rated CY14B101K = 25°C) ... 1.0W Ambient Temperature 0°C to +70°C 2.7V to 3.6V –40°C to +85°C Commercial Industrial –1... -
Page 16: Thermal Resistance
Description Description Test Conditions = 25°C, f = 1 MHz, = 0 to 3.0 V Test Conditions Figure 7. AC Test Loads 3.0V OUTPUT 5 pF 789Ω CY14B101K Unit Years Unit 48-SSOP Unit °C/W 34.85 °C/W 16.35 R1 577Ω For Tri-state Specs 789Ω... - Page 17 14. These parameters are guaranteed by design and are not tested. 15. HSB must remain HIGH during READ and WRITE cycles. Document Number: 001-06401 Rev. *I 25 ns Description CY14B101K 35 ns 45 ns Unit [11, 12, 15] [11, 15]...
- Page 18 Document Number: 001-06401 Rev. *I (continued) 25 ns Description DATA VALID HZWE HIGH IMPEDANCE Figure 11. SRAM Write Cycle 2: CE Controlled DATA VALID HIGH IMPEDANCE CY14B101K 35 ns 45 ns Unit [15, 17] LZWE Page 18 of 28 [+] Feedback...
- Page 19 19. If an SRAM Write does not taken place since the last nonvolatile cycle, no STORE takes place. 20. Industrial Grade Devices require 15 ms Max. Document Number: 001-06401 Rev. *I Commercial Industrial Figure 12. AutoStore/Power Up RECALL STORE HRECALL SWITCH CY14B101K CY14B101K Unit 12.5 2.65 μs STORE occurs only No STORE occurs if a SRAM write...
- Page 20 22. The six consecutive addresses are read in the order listed in the Document Number: 001-06401 Rev. *I [21, 22] 25 ns DATA VALID DATA VALID Table 2 on page 6. WE is HIGH during all six consecutive cycles. CY14B101K 35 ns 45 ns Unit [22] STORE RECALL HIGH IMPEDANCE...
- Page 21 24. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command. 25. Read and Write cycles in progress before HSB are given this amount of time to complete. Document Number: 001-06401 Rev. *I Description Figure 15. Hardware STORE Cycle Figure 16. Soft Sequence Processing CY14B101K CY14B101K Unit μs CY14B101K Unit μs...
- Page 22 Test Conditions At Min Temperature from Power up or Enable At 25°C Temperature from Power up or Enable Mode Deselect/Power down –DQ Read Output Disabled –DQ Write CY14B101K Unit Commercial Industrial Power Standby Active Active Active Page 22 of 28...
-
Page 23: Part Numbering Nomenclature
I - Industrial (–40 to 85°C) Package: SP - 48 SSOP Data Bus: K - x8 + RTC Voltage: B - 3.0V CY14B101K Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns Density: 101 - 1 Mb... -
Page 24: Ordering Information
Ordering Information All the below mentioned parts are Pb-free. Please contact your local Cypress sales representative for availability of these parts. Speed (ns) Ordering Code CY14B101K-SP25XC CY14B101K-SP25XCT CY14B101K-SP25XI CY14B101K-SP25XIT CY14B101K-SP35XC CY14B101K-SP35XCT CY14B101K-SP35XI CY14B101K-SP35XIT CY14B101K-SP45XC CY14B101K-SP45XCT CY14B101K-SP45XI CY14B101K-SP45XIT Document Number: 001-06401 Rev. *I... -
Page 25: Package Diagrams
CY14B101K Package Diagrams Figure 17. 48-Pin Shrunk Small Outline Package (51-85061) 51-85061-*C Document Number: 001-06401 Rev. *I Page 25 of 28 [+] Feedback... - Page 26 Document History Page Document Title: CY14B101K 1 Mbit (128K x 8) nvSRAM With Real Time Clock Document Number: 001-06401 REV. ECN NO. Orig. of Change 425138 437321 471966 503272 597002 688776 1349963 UHA/SFV 1739984 vsutmp8/AESA 2427986 GVCH/PYRS Document Number: 001-06401 Rev. *I...
- Page 27 Document Title: CY14B101K 1 Mbit (128K x 8) nvSRAM With Real Time Clock Document Number: 001-06401 REV. ECN NO. Orig. of Change 2663934 GVCH/PYRS Document Number: 001-06401 Rev. *I Submission Description of Change Date 02/24/09 Updated Features Updated pin definition of WE...
- Page 28 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. PSoC Solutions psoc.cypress.com General clocks.cypress.com Low Power/Low Voltage Precision Analog LCD Drive image.cypress.com CAN 2.0b Revised February 24, 2009 CY14B101K psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page 28 of 28 [+] Feedback...
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