Cypress Semiconductor MoBL CY62148BN Specification Sheet

Features
• High Speed
— 70 ns
• 4.5V–5.5V operation
• Low active power
— Typical active current: 2.5 mA @ f = 1 MHz
— Typical active current:12.5 mA @ f = f
• Low standby current
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• CMOS for optimum speed/power
• Available in standard lead-free and non-lead-free
32-lead (450-mil) SOIC, 32-lead TSOP II and 32-lead
Reverse TSOP II packages
Logic Block Diagram
A
A
A
A
CE
WE
OE
Cypress Semiconductor Corporation
Document #: 001-06517 Rev. *A
(70 ns)
max
INPUT BUFFER
A
0
A
1
A
4
A
5
A
6
512 K x 8
A
7
ARRAY
12
14
16
17
COLUMN
DECODER
• 198 Champion Court
4-Mbit (512K x 8) Static RAM
Functional Description
The CY62148BN is a high-performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that reduces power
consumption by more than 99% when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O through I/O
0 7
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
POWER
DOWN
,
• San Jose CA 95134-1709
CY62148BN MoBL
) is then written into the location
through A ).
0 18
through I/O ) are placed in a
0 7
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
• 408-943-2600
Revised August 2, 2006
®
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