Cypress Semiconductor CY8C24223A Specification Sheet
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Cypress Semiconductor CY8C24223A Specification Sheet

Psoc programmable system-on-chip
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Features
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds to 12 MHz
❐
8x8 Multiply, 32-Bit Accumulate
❐
Low Power at High Speed
❐
4.75V to 5.25V Operating Voltage
❐
Extended Temperature Range: -40°C to +125°C
■
Advanced Peripherals (PSoC Blocks)
❐
Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐
Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐
Complex Peripherals by Combining Blocks
■
Precision, Programmable Clocking
❐
Internal ± 4% 24 MHz Oscillator
❐
High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐
Optional External Oscillator, up to 24 MHz
❐
Internal Oscillator for Watchdog and Sleep
■
Flexible On-Chip Memory
❐
4K Bytes Flash Program Storage 100 Erase/Write Cycles
❐
256 Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP)
❐
Partial Flash Updates
❐
Flexible Protection Modes
■
Programmable Pin Configurations
❐
25 mA Sink on All GPIO
❐
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐
Up to Ten Analog Inputs on GPIO
❐
Two 30 mA Analog Outputs on GPIO
❐
Configurable Interrupt on All GPIO
Cypress Semiconductor Corporation
Document Number: 3-12029 Rev. *E
®
PSoC
Programmable System-on-Chip™
■
Additional System Resources
❐
I
❐
Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
■
Complete Development Tools
❐
Free Development Software (PSoC Designer™)
❐
Full-Featured, In-Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Bytes Trace Memory
Logic Block Diagram
•
198 Champion Court
CY8C24223A, CY8C24423A
2
C™ Slave, Master, and Multi-Master to 400 kHz
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
SROM
Flash 4K
256 Bytes
CPU Core (M8C)
Interrupt
Controller
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Digital
Block Array
(1 Row,
(2 Columns,
4 Blocks)
6 Blocks)
Digital
Multiply
Decimator
2
I
C
Clocks
Accum.
SYSTEM RESOURCES
,
•
San Jose
CA 95134-1709
Analog
Port 2
Port 1
Port 0
Drivers
Global Analog Interconnect
Sleep and
Watchdog
Analog
Analog
Ref
Block
Array
Analog
Input
Muxing
POR and LVD
Internal
Voltage
System Resets
Ref.
•
408-943-2600
Revised December 11, 2008
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Summary of Contents for Cypress Semiconductor CY8C24223A

  • Page 1 Digital Block Array (1 Row, 4 Blocks) Digital Multiply Clocks Accum. • 198 Champion Court • San Jose CY8C24223A, CY8C24423A Analog Port 2 Port 1 Port 0 Drivers Global Analog Interconnect SROM Flash 4K CPU Core (M8C) Sleep and Watchdog...

  • Page 2: Functional Overview

    Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A Digital System The Digital System is composed of four digital PSoC blocks.

  • Page 3: Analog System

    Analog blocks are arranged in a column of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in Figure Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A Figure 2. Analog System Block Diagram P0[7] P0[5] P0[3]...

  • Page 4: Getting Started

    Design Resources list located in the center of the web Bytes page. Application notes are listed by date as default. Bytes Bytes Bytes CY8C24223A, CY8C24423A web site and select Application Notes Page 4 of 31 [+] Feedback...

  • Page 5: Development Tools

    C tailored to the PSoC architecture. It comes complete with Device embedded libraries providing port and bus operations, standard Programmer keypad and display support, and extended math functionality. CY8C24223A, CY8C24423A dynamic reconfiguration. Dynamic Page 5 of 31 [+] Feedback...

  • Page 6: Hardware Tools

    For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time.

  • Page 7: Document Conventions

    ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. CY8C24223A, CY8C24423A Description on page 10 lists all the abbreviations used to ‘b’ (for example, 01010100b’...
  • Page 8 * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details. Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A Figure 5. CY8C24223A 20-Pin PSoC Device Description A, I, P0[7] A, IO, P0[5]...
  • Page 9 A, IO, P0[3] A, I, P0[1] A, I, P2[3] A, I, P2[1] I2C SCL, P1[7] I2C SDA, P1[5] I2C SCL, XTALin, P1[1] CY8C24223A, CY8C24423A P0[6], A, I P0[4], A, I P0[2], A, I P2[7] P0[0], A, I P2[5] P2[6], External VRef...

  • Page 10: Register Reference

    Clearable register or bit(s) Access is bit specific Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks.
  • Page 11 DBB01DR1 ASY_CR DBB01DR2 CMP_CR1 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 Blank fields are Reserved and must not be accessed. Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0...
  • Page 12 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 Blank fields are Reserved and must not be accessed. Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 # Access is bit specific. ASC10CR0 ASC10CR1 ASC10CR2...
  • Page 13 DCB03OU ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 Blank fields are Reserved and must not be accessed. Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A ASC21CR3 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 # Access is bit specific. OSC_GO_EN OSC_CR4...

  • Page 14: Electrical Specifications

    12 MHz CPU Frequency Symbol μW microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts CY8C24223A, CY8C24423A 24 MHz Unit of Measure Page 14 of 31 [+] Feedback...

  • Page 15: Absolute Maximum Ratings

    Operating Temperature Table 10. Operating Temperature Symbol Description Ambient Temperature Junction Temperature Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A Units +125 Higher storage temperatures reduce data retention time. Recommended storage temper- ature is +25°C ± 25°C. Storage temperatures above 65 degrades reliability.

  • Page 16: Dc Electrical Characteristics

    – – – – – – – – CY8C24223A, CY8C24423A Units Notes C ≤ T Conditions are Vdd = 5.25V, -40 ≤ 125 C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off.
  • Page 17 Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High PSRR Supply Voltage Rejection Ratio Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A Units – – – μV/ – 35.0 Gross tested to 1 μA...
  • Page 18 Low Output Voltage Swing (Load = 32 ohms to Vdd/2) OLOWOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRR Supply Voltage Rejection Ratio Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A – Vdd - 1 – – – – –...
  • Page 19 P2[6] + 2.4 P2[4] + 1.24 P2[4] + P2[6] - 0.1 /2 - 1.45 1.15 2.4 - P2[6] P2[4] - 1.45 P2[4] - P2[6] - 0.1 CY8C24223A, CY8C24423A Units 1.30 1.35 Vdd/2 Vdd/2 + 0.02 P2[4] P2[4] + 0.02 1.30 1.37...
  • Page 20 4.62 4.710 4.75 – – – – – 6,400 AN2015 http://www.cypress.com under Application Notes for more information. ≤ 125°C and the remaining time at T CY8C24223A, CY8C24423A Units 12.24 – kΩ – Units 4.55 4.70 4.55 – 4.73 4.83 4.814 4.950...

  • Page 21: Ac Electrical Characteristics

    Maximum frequency of signal on row input or row output. Supply Ramp Time RAMP a. See the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A Units 22.95 24.96 Trimmed. Using factory trim values.
  • Page 22 Select 32K2 Figure 11. 24 MHz Period Jitter (IMO) Timing Diagram Figure 12. 32 kHz Period Jitter (ECO) Timing Diagram 32K2 Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A Figure 8. PLL Lock Timing Diagram PLLSLEW PLLSLEWLOW Jitter24M1 Jitter32k 24 MHz...
  • Page 23 Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A – 12.48 – – – –...
  • Page 24 10000 1000 0.001 Document Number: 3-12029 Rev. *E – – 0.01 Freq (kHz) Figure 15. Typical Opamp Noise 0.01 Freq (kHz) CY8C24223A, CY8C24423A Units Notes μs ≥ 50 mV overdrive comparator reference set within V REFLPC 0.01 PH_BH PH_BL PM_BL...
  • Page 25 Maximum Input Clock Frequency Receiver Maximum Input Clock Frequency a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A Units 24.96 – –...
  • Page 26 WRITE Data Out Delay from Falling Edge of SCLK DSCLK Document Number: 3-12029 Rev. *E Description , 3dB BW, 100 pF Load , 3dB BW, 100 pF Load Description Description CY8C24223A, CY8C24423A Units μs – – μs – – μs –...
  • Page 27 SU;DAT Figure 16. Definition for Timing for Fast/Standard Mode on the I2C Bus LOWI2C HDDATI2C HDSTAI2C Document Number: 3-12029 Rev. *E Standard Mode SUDATI2C HDSTAI2C SUSTAI2C HIGHI2C CY8C24223A, CY8C24423A Fast Mode – – – – – – – – –...

  • Page 28: Packaging Information

    CY8C24223A, CY8C24423A Packaging Information This section illustrates the packaging specifications for the CY8C24x23A automotive PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’...
  • Page 29 Capacitance on Crystal Pins Table 30. Typical Package Capacitance on Crystal Pins Typical θ Package 20 SSOP 28 SSOP Maximum Peak Temperature CY8C24223A, CY8C24423A 51-85079 *C Package Capacitance 2.6 pF 2.8 pF C with Page 29 of 31 [+] Feedback...

  • Page 30: Ordering Information

    Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). Ordering Code Definitions CY 8 C 24 xxx-12xx Document Number: 3-12029 Rev. *E CY8C24223A, CY8C24423A -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C...
  • Page 31 Update CY branding and QFN convention. Update copyright and trademarks. Post to www.cypress.com Changed title to “CY8C24223A, CY8C24423A PSoC® Programmable System-on-Chip™” Added note on digital signaling in Added Die Sales information note to Updated data sheet template.

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