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Features
True Dual-Ported memory cells that enable simultaneous reads
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of the same memory location
4K x 8 organization (CY7C138)
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4K x 9 organization (CY7C139)
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0.65-micron CMOS for optimum speed and power
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High speed access: 15 ns
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Low operating power: I
= 160 mA (max.)
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CC
Fully asynchronous operation
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Automatic power down
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TTL compatible
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Expandable data bus to 32/36 bits or more using
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Master/Slave chip select when using more than one
device
On-chip arbitration logic
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Semaphores included to permit software handshaking
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between ports
INT flag for port-to-port communication
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Available in 68-pin PLCC
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Pb-free packages available
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Logic Block Diagram
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
Document #: 38-06037 Rev. *D
4K x 8/9 Dual-Port Static RAM
Functional Description
The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and
4K x 9 dual-port static RAMs. Various arbitration schemes are
included on the CY7C138/9 to handle situations when multiple
processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C138/9 can
be used as a standalone 8/9-bit dual-port static RAM or multiple
devices can be combined to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16/18-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multipro-
cessor designs, communications status buffering, and dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip enable (CE) pin or SEM pin.
The CY7C138 and CY7C139 are available in a 68-pin PLCC.
•
198 Champion Court
CY7C138, CY7C139
with Sem, Int, Busy
,
•
San Jose
CA 95134-1709
•
408-943-2600
Revised March 12, 2009
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Related Manuals for Cypress Semiconductor CY7C138
Summary of Contents for Cypress Semiconductor CY7C138
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Page 1: Functional Description
Document #: 38-06037 Rev. *D 4K x 8/9 Dual-Port Static RAM Functional Description The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and 4K x 9 dual-port static RAMs. Various arbitration schemes are included on the CY7C138/9 to handle situations when multiple processors access the same piece of data. -
Page 2: Pin Configurations
FFF and is cleared when right port reads location FFF. Busy Flag Master or Slave Select Power Ground 7C138-15 7C138-25 7C139-15 7C139-25 CY7C138, CY7C139 BUSY BUSY pin is used when is set when left port writes location 7C138-35 7C138-55 Unit 7C139-35... -
Page 3: Maximum Ratings
One Port Commercial or CE > V – 0.2V, Industrial > V – 0.2V or < 0.2V, Active Port Outputs, f = f CY7C138, CY7C139 Ambient Temperature ° ° C to +70 5V ± 10% ° ° –40 C to +85 5V ±... - Page 4 > V – 0.2V, Industrial > V – 0.2V or < 0.2V, Active Port Outputs, f = f Test Conditions = 25°C, f = 1 MHz, = 5.0V CY7C138, CY7C139 7C138-35 7C138-55 7C139-35 7C139-55 Unit μA –10 –10 μA –10 –10...
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Page 5: Switching Characteristics
(b) Thé venin Equivalent ( Load 1) ALL INPUT PULSES 3.0V < 3 ns < 3 ns 7C138-15 7C138-25 7C139-15 7C139-25 CY7C138, CY7C139 R1 = 893Ω OUTPUT C = 5 pF R2 = 347Ω (c) Three-State Delay (Load 3) 7C138-35 7C138-55 7C139-35... -
Page 6: Interrupt Timing
Note 15 Note 15 is less than t and t HZCE LZCE HZOE – t (actual) or t – t (actual). CY7C138, CY7C139 7C138-35 7C138-55 7C139-35 7C139-55 Unit Note 15 Note 15 [16, 17] DATA VALID [16, 18, 19] is less than t... - Page 7 = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores. Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port) Document #: 38-06037 Rev. *D LZOE DATA VALID MATCH VALID MATCH CY7C138, CY7C139 HZCE HZOE [20, 21] VALID [22, 23, 24] Page 7 of 17 [+] Feedback...
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Page 8: High Impedance
HIGH IMPEDANCE DATA VALID HZWE HIGH IMPEDANCE . If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not CY7C138, CY7C139 LZOE [22, 24, 25] LZWE or (t ) to allow the I/O drivers to turn off... - Page 9 Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH) Document #: 38-06037 Rev. *D VALID ADDRESS DATA VALID SWRD WRITE CYCLE READ CYCLE MATCH MATCH CY7C138, CY7C139 DATA VALID [27, 28, 29] [21] Page 9 of 17 [+] Feedback...
- Page 10 Figure 12. Busy Timing Diagram No. 1 (CE Arbitration) Document #: 38-06037 Rev. *D MATCH VALID MATCH = CE = HIGH CY7C138, CY7C139 VALID [30] Page 10 of 17 [+] Feedback...
- Page 11 BUSY will be asserted. Document #: 38-06037 Rev. *D ADDRESS MATCH ADDRESS MATCH or t ADDRESS MISMATCH or t ADDRESS MISMATCH CY7C138, CY7C139 [30] Page 11 of 17 [+] Feedback...
- Page 12 Document #: 38-06037 Rev. *D Figure 14. Interrupt Timing Diagrams WRITE FFF [31] [32] WRITE FFE [31] [32] [32] ) is deasserted first. or R/W ) is asserted last. CY7C138, CY7C139 READ FFF READ FFE Page 12 of 17 [+] Feedback...
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Page 13: Functional Description
Architecture The CY7C138/9 consists of an array of 4K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simulta- neous writes and reads to the same location, a BUSY pin is provided on each port. - Page 14 No change. Left port is denied access Left port obtains semaphore No port accessing semaphore address Right port obtains semaphore No port accessing semaphore Left port obtains semaphore No port accessing semaphore CY7C138, CY7C139 Operation Right Port 0-11 Status Page 14 of 17 [+] Feedback...
- Page 15 OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 = 4.5V = 25°C 1000 CAPACITANCE (pF) CY7C138, CY7C139 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE = 5.0V = 25°C OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE = 5.0V = 25°C OUTPUT VOLTAGE (V) = 5.0V...
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Page 16: Ordering Information
68-Lead Pb-Free Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Pb-Free Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier CY7C138, CY7C139 Operating Range Commercial Commercial Industrial Commercial... - Page 17 Document History Page Document Title: CY7C138/CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06037 Orig. of Rev. ECN No. Change 110180 122287 393403 2623658 VKN/PYRS 2672737 GNKK Sales, Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors.
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