Cypress Semiconductor NoBL CY7C1370DV25 Manual

Cypress Semiconductor NoBL CY7C1370DV25 Manual

18-mbit (512k x 36/1m x 18) pipelined sram with nobl architecture

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Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V core power supply (V
• 2.5V I/O power supply (V
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in JEDEC-standard lead-free 100-Pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165-Ball
FBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• "ZZ" Sleep Mode option and Stop Clock option
Logic Block Diagram-CY7C1370DV25 (512K x 36)
A0, A1, A
MODE
CLK
C
CEN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
Cypress Semiconductor Corporation
Document #: 38-05558 Rev. *D
Pipelined SRAM with NoBL™ Architecture
)
DD
)
DDQ
ADDRESS
REGISTER 0
A1
D1
A0
BURST
D0
LOGIC
ADV/LD
C
WRITE ADDRESS
WRITE ADDRESS
REGISTER 1
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
198 Champion Court
18-Mbit (512K x 36/1M x 18)
Functional Description
The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x
36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1370DV25 and
CY7C1372DV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1370DV25
and CY7C1372DV25 are pin-compatible and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
–BW
for
CY7C1370DV25
a
d
CY7C1372DV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
A1'
Q1
A0'
Q0
S
E
N
S
E
MEMORY
WRITE
ARRAY
A
DRIVERS
M
P
S
E
INPUT
E
REGISTER 1
,
San Jose
CA 95134-1709
CY7C1370DV25
CY7C1372DV25
and
BW
–BW
a
, CE
, CE
) and an
1
2
3
O
D
U
A
T
P
T
U
A
T
S
B
DQs
U
T
DQP
a
F
E
DQP
F
b
E
DQP
E
c
R
R
DQP
d
I
S
N
E
G
INPUT
E
REGISTER 0
408-943-2600
Revised June 29, 2006
for
b
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Summary of Contents for Cypress Semiconductor NoBL CY7C1370DV25

  • Page 1 Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200 and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE •...
  • Page 2: Selection Guide

    Logic Block Diagram-CY7C1372DV25 (1M x 18) ADDRESS A0, A1, A REGISTER 0 MODE WRITE ADDRESS REGISTER 1 ADV/LD READ LOGIC Sleep Control Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Document #: 38-05558 Rev. *D BURST LOGIC ADV/LD WRITE ADDRESS...
  • Page 3: Pin Configurations

    Pin Configurations DQPc CY7C1370DV25 (512K × 36) DQPd Document #: 38-05558 Rev. *D 100-Pin TQFP Pinout DQPb CY7C1372DV25 (1M × 18) DQPb DQPa CY7C1370DV25 CY7C1372DV25 DQPa Page 3 of 27 [+] Feedback...
  • Page 4 Pin Configurations (continued) NC/576M NC/1G NC/144M NC/576M NC/1G NC/144M NC/72M Document #: 38-05558 Rev. *D 119-Ball BGA Pinout CY7C1370DV25 (512K × 36) ADV/LD MODE NC/72M CY7C1372DV25 (1M x 18) ADV/LD MODE NC/36M CY7C1370DV25 CY7C1372DV25 NC/288M NC/36M NC/288M Page 4 of 27 [+] Feedback...
  • Page 5 Pin Configurations (continued) NC/576M NC/1G NC/144M NC/72M MODE NC/36M NC/576M NC/1G NC/144M NC/72M MODE NC/36M Document #: 38-05558 Rev. *D 165-Ball FBGA Pinout CY7C1370DV25 (512K × 36) CY7C1372DV25 (1M × 18) CY7C1370DV25 CY7C1372DV25 ADV/LD NC/288M ADV/LD NC/288M Page 5 of 27 [+] Feedback...
  • Page 6: Pin Definitions

    Pin Definitions Pin Name I/O Type Input- Address Inputs used to select one of the address locations. Sampled at the rising edge of Synchronous the CLK. Input- Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Synchronous Sampled on the rising edge of CLK.
  • Page 7 Pin Definitions (continued) Pin Name I/O Type Power Supply Power supply inputs to the core of the device. I/O Power Power supply for the I/O circuitry. Supply Ground Ground for the device. Should be connected to ground of the system. –...
  • Page 8 signals. The CY7C1370DV25/CY7C1372DV25 provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered.
  • Page 9: Truth Table

    [1, 2, 3, 4, 5, 6, 7] Truth Table Operation Deselect Cycle None Continue Deselect Cycle None Read Cycle (Begin Burst) External Read Cycle (Continue Burst) Next NOP/Dummy Read (Begin Burst) External Dummy Read (Continue Burst) Next Write Cycle (Begin Burst) External Write Cycle (Continue Burst) Next...
  • Page 10: Tap Controller State Diagram

    Function (CY7C1372DV25) Read Write – No Bytes Written Write Byte a – (DQ and DQP Write Byte b – (DQ and DQP Write Both Bytes IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1370DV25/CY7C1372DV25 incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1.
  • Page 11 TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK.
  • Page 12 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
  • Page 13 TAP AC Switching Characteristics Parameter Clock TCK Clock Cycle Time TCYC TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time Output Times TCK Clock LOW to TDO Valid TDOV TCK Clock LOW to TDO Invalid TDOX Set-up Times TMS Set-up to TCK Clock Rise TMSS TDI Set-up to TCK Clock Rise...
  • Page 14 2.5V TAP AC Test Conditions Input pulse levels ... V Input rise and fall time... 1 ns Input timing reference levels ...1.25V Output reference levels...1.25V Test load termination supply voltage...1.25V TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; V = 2.5V ±0.125V unless otherwise noted) Parameter Description...
  • Page 15: Identification Codes

    Identification Codes Instruction Code EXTEST Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO.
  • Page 16 165-Ball FBGA Boundary Scan Order Bit # Ball ID Note: 14. Bit# 89 is pre-set HIGH. Document #: 38-05558 Rev. *D [12, 14] Bit # Ball ID CY7C1370DV25 CY7C1372DV25 Bit # Ball ID Internal Page 16 of 27 [+] Feedback...
  • Page 17 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ... –65°C to +150°C Ambient Temperature with Power Applied... –55°C to +125°C Supply Voltage on V Relative to GND... –0.5V to +3.6V Supply Voltage on V Relative to GND ...
  • Page 18 [17] Capacitance Parameter Description Input Capacitance Clock Input Capacitance Input/Output Capacitance [17] Thermal Resistance Parameter Description Θ Thermal Resistance (Junction to Ambient) Θ Thermal Resistance (Junction to Case) AC Test Loads and Waveforms 2.5V I/O Test Load OUTPUT OUTPUT = 50Ω = 50Ω...
  • Page 19: Switching Characteristics

    Switching Characteristics Over the Operating Range Parameter Description [18] (typical) to the first access read or write Power Clock Clock Cycle Time Maximum Operating Frequency Clock HIGH Clock LOW Output Times Data Output Valid After CLK Rise OE LOW to Output Valid Data Output Hold After CLK Rise [19, 20, 21] Clock to High-Z...
  • Page 20: Switching Waveforms

    Switching Waveforms [24, 25, 26] Read/Write/Timing t CYC CENS CENH ADV/LD ADDRESS Data In-Out (DQ) WRITE WRITE D(A1) D(A2) Notes: 24. For this waveform ZZ is tied LOW. 25. When CE is LOW, CE is LOW, CE is HIGH and CE 26.
  • Page 21 Switching Waveforms (continued) [24, 25, 27] NOP,STALL and DESELECT Cycles ADV/LD ADDRESS Data In-Out (DQ) WRITE READ STALL D(A1) Q(A2) [28, 29] ZZ Mode Timing SUPPLY I DDZZ ALL INPUTS (except ZZ) Outputs (Q) Notes: 27. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle 28.
  • Page 22: Ordering Information

    Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit Speed Package (MHz) Ordering Code Diagram CY7C1370DV25-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1372DV25-167AXC CY7C1370DV25-167BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
  • Page 23 Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit CY7C1370DV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1372DV25-250AXC CY7C1370DV25-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-250BGC CY7C1370DV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1372DV25-250BGXC...
  • Page 24: Package Diagrams

    Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050) R 0.08 MIN. 0° MIN. 0.20 MAX. 0.25 GAUGE PLANE R 0.08 MIN. 0°-7° 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05558 Rev. *D 16.00±0.20 14.00±0.10 0.30±0.08...
  • Page 25 CY7C1370DV25 CY7C1372DV25 Package Diagrams (continued) 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) 51-85115-*B Document #: 38-05558 Rev. *D Page 25 of 27 [+] Feedback...
  • Page 26 Package Diagrams (continued) TOP VIEW TOP VIEW PIN 1 CORNER PIN 1 CORNER 13.00±0.10 13.00±0.10 SEATING PLANE SEATING PLANE NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05558 Rev.
  • Page 27 Document History Page Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05558 REV. ECN No. Issue Date 254509 See ECN 288531 See ECN 326078 See ECN 418125 See ECN 475677 See ECN Document #: 38-05558 Rev.

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