Cypress Semiconductor CY7C1380C Specification Sheet

Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 225, 200,166 and
133MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 166-MHz device)
— 4.2 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
and 165-Ball fBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• "ZZ" Sleep Mode Option
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE , CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
3 2
Cypress Semiconductor Corporation
Document #: 38-05237 Rev. *D
18-Mb (512K x 36/1M x 18) Pipelined SRAM
Functional Description
The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable ( CE
Enables (CE
and ADV ), Write Enables ( BW
( GW ). Asynchronous inputs include the Output Enable ( OE )
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor ( ADSP ) or
Address Strobe Controller ( ADSC ) are active. Subsequent
burst addresses can be internally generated as controlled by
®
the Advance pin ( ADV ).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1380C/CY7C1382C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
250 MHz 225 MHz
2.6
350
70
• 3901 North First Street
[1]
[2]
and CE ), Burst Control inputs ( ADSC , ADSP ,
2
3
X
200 MHz 167 MHz
2.8 3.0 3.4
325 300 275
70 70 70
,
• San Jose CA 95134
CY7C1380C
CY7C1382C
), depth-expansion Chip
1
, and BWE ), and Global Write
133 MHz Unit
4.2 ns
245 mA
70 mA
• 408-943-2600
Revised February 26, 2004
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