Cypress Semiconductor CY7C1354CV25 Specification Sheet

Features
• Pin-compatible with and functionally equivalent to
ZBT™
• Supports 250-MHz bus operations with zero wait states
• Available speed grades are 250, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply (V
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability–linear or interleaved burst order
• "ZZ" Sleep Mode option and Stop Clock option
Logic Block Diagram–CY7C1354CV25 (256K x 36)
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05537 Rev. *H
Pipelined SRAM with NoBL™ Architecture
)
DD
ADDRESS
REGISTER 0
A1 A1'
D1 Q1
A0 BURST A0'
D0 Q0
LOGIC
ADV/LD
C
WRITE ADDRESS WRITE ADDRESS
REGISTER 1 REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
• 198 Champion Court
9-Mbit (256K x 36/512K x 18)
Functional Description
The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1354CV25 and
CY7C1356CV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1354CV25
and CY7C1356CV25 are pin-compatible with and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW –BW for CY7C1354CV25
a d
CY7C1356CV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
S
D
E
A
N
T
S
A
E
MEMORY S
WRITE
ARRAY
A T
DRIVERS
E
M
E
P
R
S
I
N
E
G
INPUT INPUT
E E
REGISTER 1 REGISTER 0
,
• San Jose CA 95134-1709
CY7C1354CV25
CY7C1356CV25
[1]
and BW –BW for
a b
, CE , CE ) and an
1 2 3
O
U
T
P
U
T
B
DQs
U
DQP
a
F
DQP
b
F
DQP
E c
R DQP
d
S
E
• 408-943-2600
Revised September 14, 2006
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