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Cypress Semiconductor CY7C09089V Specification Sheet

3.3v 32k/64k/128k x 8/9 synchronous dual-port static ram
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CY7C09079V/89V/99V
CY7C09179V/89V/99V
Features
True Dual-Ported memory cells which enable simultaneous
■
access of the same memory location
6 Flow-Through and Pipelined devices
■
32K x 8/9 organizations (CY7C09079V/179V)
■
64K x 8/9 organizations (CY7C09089V/189V)
■
128K x 8/9 organizations (CY7C09099V/199V)
■
3 Modes
■
Flow-Through
■
Pipelined
■
Burst
■
Pipelined output mode on both ports enables fast 100 MHz
■
operation
0.35-micron CMOS for optimum speed and power
■
Logic Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
FT/Pipe
L
[2]
I/O
–I/O
0L
7/8L
15/16/17
[3]
A
–A
0
14/15/16L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Notes
1. See page 6 for Load Conditions.
2. I/O
–I/O
for x8 devices, I/O
–I/O
0
7
0
3. A
–A
for 32K, A
–A
for 64K, and A
0
14
0
15
Cypress Semiconductor Corporation
Document #: 38-06043 Rev. *C
1
0
0/1
1
0
0/1
8/9
I/O
Control
Counter/
Address
True Dual-Ported
Register
Decode
for x9 devices.
8
–A
for 128K devices.
0
16
•
198 Champion Court
3.3V 32K/64K/128K x 8/9
Synchronous Dual-Port Static RAM
High speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.)
■
3.3V low operating power
■
Active= 115 mA (typical)
■
Standby= 10 μA (typical)
■
Fully synchronous interface for easier operation
■
Burst counters increment addresses internally
■
Shorten cycle times
■
Minimize bus noise
■
Supported in Flow-Through and Pipelined modes
■
Dual Chip Enables for easy depth expansion
■
Automatic power down
■
Commercial and Industrial temperature ranges
■
Available in 100-pin TQFP
■
Pb-free packages available
■
I/O
Control
RAM Array
•
San Jose
CY7C09079V/89V/99V
CY7C09179V/89V/99V
1
0
0/1
0
1
0/1
8/9
I/O
0R
15/16/17
A
–A
0
Counter/
Address
Register
Decode
CNTRST
,
CA 95134-1709
•
408-943-2600
Revised December 10, 2008
R/W
R
OE
R
CE
0R
CE
1R
FT/Pipe
R
[2]
–I/O
7/8R
[3]
14/15/16R
CLK
R
ADS
R
CNTEN
R
R
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Summary of Contents for Cypress Semiconductor CY7C09089V

  • Page 1 True Dual-Ported memory cells which enable simultaneous ■ access of the same memory location 6 Flow-Through and Pipelined devices ■ 32K x 8/9 organizations (CY7C09079V/179V) ■ 64K x 8/9 organizations (CY7C09089V/189V) ■ 128K x 8/9 organizations (CY7C09099V/199V) ■ 3 Modes ■ Flow-Through ■...

  • Page 2: Functional Description

    LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to enable the shortest possible cycle times. Pin Configurations Figure 1. 100-Pin TQFP (Top View) - CY7C09099V (128K x 8), CY7C09089V (64K x 8),CY7C09079V (32K x 8) A10L A11L...
  • Page 3 Pin Configurations (continued Figure 2. 100-Pin TQFP (Top View0 - CY7C09199V (128K x 9), CY7C09189V (64K x 9),CY7C09179V (32K x 9) A10L A11L A12L A13L A14L A15L A16L CE0L CE1L CNTRSTL R/WL FT/PIPEL Document #: 38-06043 Rev. *C 92 91 90 87 86 83 82 81 34 35 36...

  • Page 4: Pin Definitions

    Selection Guide CY7C09079V/89V/99V Description CY7C09179V/89V/99V-6 (MHz) MAX2 (Pipelined) Max. Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current I (mA) Typical Standby Current for I (mA) (Both Ports TTL Level) 10 μA Typical Standby Current for I (μA) (Both Ports CMOS Level) Pin Definitions Left Port...

  • Page 5: Maximum Ratings

    Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ... –65 Ambient Temperature with Power Applied.. –55 Supply Voltage to Ground Potential...–0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ...
  • Page 6 3.3V R1 = 590Ω OUTPUT C = 30 pF R2 = 435Ω (a) Normal Load (Load 1) Figure 4. AC Test Loads (Applicable to -6 and -7 only) = 50Ω R = 50Ω OUTPUT = 1.4V (a) Load 1 (-6 and -7 only) 0.

  • Page 7: Switching Characteristics

    Switching Characteristics Over the Operating Range Parameter Description Flow-Through MAX1 Pipelined MAX2 Clock Cycle Time - Flow-Through CYC1 Clock Cycle Time - Pipelined CYC2 Clock HIGH Time - Flow-Through Clock LOW Time - Flow-Through Clock HIGH Time - Pipelined Clock LOW Time - Pipelined Clock Rise Time Clock Fall Time Address Set-Up Time...

  • Page 8: Switching Waveforms

    Switching Waveforms (continued) Figure 6. Read Cycle for Flow-Through Output (FT/PIPE = V ADDRESS DATA CKLZ Notes 16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 17. ADS = V , CNTEN and CNTRST = V 18.
  • Page 9 Switching Waveforms (continued) Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = V CYC2 ADDRESS 1 Latency DATA Figure 8. Bank Select Pipelined Read CYC2 ADDRESS (B1) 0(B1) DATA OUT(B1) ADDRESS (B2) 0(B2) DATA OUT(B2) Document #: 38-06043 Rev. *C CKLZ [20, 21] CKHZ...
  • Page 10 Switching Waveforms (continued) Figure 9. Left Port Write to Flow-Through Right Port Read ADDRESS MATCH VALID DATA MATCH ADDRESS DATA OUTR Notes 20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS = ADDRESS (B2) 21.
  • Page 11 Switching Waveforms (continued) Figure 10. Pipelined Read-to-Write-to-Read (OE = V CYC2 ADDRESS DATA DATA READ Document #: 38-06043 Rev. *C CKHZ NO OPERATION CY7C09079V/89V/99V CY7C09179V/89V/99V [19, 26, 27, 28] CKLZ WRITE READ Page 11 of 21 [+] Feedback...
  • Page 12 Switching Waveforms (continued) Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled) CYC2 ADDRESS DATA DATA READ Notes 26. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 27. CE and ADS = V ; CE , CNTEN, and CNTRST = V 28.
  • Page 13 Switching Waveforms (continued) Figure 12. Flow-Through Read-to-Write-to-Read (OE = V CYC1 ADDRESS DATA DATA Figure 13. Flow-Through Read-to-Write-to-Read (OE Controlled) CYC1 ADDRESS DATA DATA Document #: 38-06043 Rev. *C CKHZ READ OPERATION READ WRITE CY7C09079V/89V/99V CY7C09179V/89V/99V [17, 19, 26, 27, 28] CKLZ WRITE READ...
  • Page 14 Switching Waveforms (continued) Figure 14. Pipelined Read with Address Counter Advance CYC2 ADDRESS CNTEN DATA READ EXTERNAL ADDRESS Figure 15. Flow-Through Read with Address Counter Advance CYC1 ADDRESS CNTEN DATA READ EXTERNAL ADDRESS Note 29. CE and OE = V ;...
  • Page 15 Switching Waveforms (continued) Figure 16. Write with Address Counter Advance (Flow-Through or Pipelined Outputs) CYC2 ADDRESS INTERNAL ADDRESS CNTEN DATA WRITE EXTERNAL ADDRESS Notes 30. CE and R/W = V ; CE and CNTRST = V 31. The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06043 Rev.
  • Page 16 Switching Waveforms (continued) Figure 17. Counter Reset (Pipelined Outputs) CYC2 ADDRESS INTERNAL ADDRESS CNTEN SRST HRST CNTRST DATA DATA COUNTER RESET Notes 32. CE ; CE 33. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06043 Rev.
  • Page 17 Table 1. Read/Write and Enable Operation Inputs Table 2. Address Counter Control Operation Previous Address CNTEN Address Notes 34. “X” = “Don’t Care”, “H” = V , “L” = V 35. ADS, CNTEN, CNTRST = “Don’t Care.” 36. OE is an asynchronous input signal. 37.

  • Page 18: Ordering Information

    32K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code CY7C09079V-6AC CY7C09079V-7AC CY7C09079V-7AI CY7C09079V-9AC CY7C09079V-12AC 64K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code CY7C09089V-6AC CY7C09089V-6AXC CY7C09089V-7AC CY7C09089V-9AC CY7C09089V-12AC CY7C09089V-12AXC CY7C09089V-12AXI 128K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code CY7C09099V-6AC...
  • Page 19 64K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code CY7C09189V-6AC CY7C09189V-6AXC CY7C09189V-7AC CY7C09189V-9AC CY7C09189V-12AC CY7C09189V-12AXC 128K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code CY7C09199V-6AC CY7C09199V-6AXC CY7C09199V-7AC CY7C09199V-7AXC CY7C09199V-9AC CY7C09199V-9AXC CY7C09199V-9AI CY7C09199V-9AXI CY7C09199V-12AC CY7C09199V-12AXC Document #: 38-06043 Rev. *C Package Name Package Type A100...

  • Page 20: Package Diagram

    Package Diagram Figure 18. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 (51-85048) Document #: 38-06043 Rev. *C CY7C09079V/89V/99V CY7C09179V/89V/99V 51-85048-*B Page 20 of 21 [+] Feedback...
  • Page 21 Added Pb-Free Logo Added Pb-Free Part Ordering Information: CY7C09089V-6AXC, CY7C09089V-12AXC, CY7C09099V-6AXC, CY7C09099V-7AI, CY7C09099V-7AXI, CY7C09099V-12AXC, CY7C09179V-6AXC, CY7C09179V-12AXC, CY7C09189V-6AXC, CY7C09189V-12AXC, CY7C09199V-6AXC, CY7C09199V-7AXC, CY7C09199V-9AXC, CY7C09199V-9AXI, CY7C09199V-12AXC Added CY7C09089V-12AXI part in the Ordering information table PSoC Solutions psoc.cypress.com General clocks.cypress.com Low Power/Low Voltage Precision Analog LCD Drive image.cypress.com...

This manual is also suitable for:

Cy7c09079vCy7c09099vCy7c09179vCy7c09189vCy7c09199v

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