Cypress Semiconductor CY7C1024DV33 Specification Sheet

Features
■ High speed
❐
t = 10 ns
AA
■ Low active power
❐ I = 175 mA at 10 ns
CC
■ Low CMOS standby power
❐ I = 25 mA
SB2
■
Operating voltages of 3.3 ± 0.3V
■
2.0V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE
■ Available in Pb-free standard 119-ball PBGA
Logic Block Diagram
A
Cypress Semiconductor Corporation
Document Number: 001-08353 Rev. *C
, CE , and CE features
1 2 3
INPUT BUFFER
128K x 24
ARRAY
(9:0)
COLUMN
DECODER
A
(16:10)
• 198 Champion Court
3-Mbit (128K X 24) Static RAM

Functional Description

The CY7C1024DV33 is a high performance CMOS static RAM
organized as 128K words by 24 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
To write to the device, enable the chip (CE
and CE LOW), while forcing the Write Enable (WE) input LOW.
3
To read from the device, enable the chip by taking CE
HIGH, and CE LOW while forcing the Output Enable (OE) LOW
3
and the Write Enable (WE) HIGH. See the
7 for a complete description of Read and Write modes.
The 24 I/O pins (I/O to I/O
0 23
state when the device is deselected (CE
CE HIGH) or when the output enable (OE) is HIGH during a
3
write operation. (CE LOW, CE
1
LOW).
CE , CE
1
WE
CONTROL LOGIC
OE
,
• San Jose CA 95134-1709
CY7C1024DV33
LOW, CE HIGH,
1 2
LOW, CE
1
Truth Table on page
) are placed in a high impedance
HIGH, CE LOW, or
1 2
HIGH, CE LOW, and WE
2 3
I/O – I/O
0 23
, CE
2 3
• 408-943-2600
Revised November 6, 2008
2
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