Cypress Semiconductor CY7C0430CV Specification Sheet

Cypress quadport dse family specification sheet

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Features

• QuadPort™ datapath switching element (DSE) family

allows four independent ports of access for data path

management and switching

• High-bandwidth data throughput up to 10 Gb/s

[1]

• 133-MHz

port speed x 18-bit-wide interface × 4 ports

• High-speed clock to data access 4.2 ns (max.)

• Synchronous pipelined device

— 1-Mb (64K × 18) switch array

• 0.25-micron CMOS for optimum speed/power

• IEEE 1149.1 JTAG boundary scan

• Width and depth expansion capabilities

• BIST (Built-In Self-Test) controller

QuadPort DSE Family Applications

Note:

1. f

for commercial is 135 MHz and for industrial is 133 MHz.

MAX2

Cypress Semiconductor Corporation

Document #: 38-06027 Rev. *B

10 Gb/s 3.3V QuadPort™ DSE Family

PORT 1

PORT 2

BUFFERED SWITCH

PORT 1

REDUNDANT DATA MIRROR

•

198 Champion Court

• Dual Chip Enables on all ports for easy depth expansion

• Separate upper-byte and lower-byte controls on all

ports

• Simple array partitioning

— Internal mask register controls counter wrap-around

— Counter-Interrupt flags to indicate wrap-around

— Counter and mask registers readback on address

• 272-ball BGA package (27-mm × 27-mm × 1.27-mm ball

pitch)

• Commercial and industrial temperature ranges

• 3.3V low operating power

— Active = 750 mA (maximum)

— Standby = 15 mA (maximum

PORT 3

PORT 4

PORT 2

PORT 3

PORT 4

•

San Jose

CA 95134-1709

CY7C0430BV

CY7C0430CV

•

408-943-2600

Revised May 23, 2006

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Page 1 — Standby = 15 mA (maximum PORT 4 BUFFERED SWITCH PORT 2 PORT 3 PORT 4 REDUNDANT DATA MIRROR • 198 Champion Court • San Jose CY7C0430BV CY7C0430CV PORT 3 CA 95134-1709 • 408-943-2600 Revised May 23, 2006 [+] Feedback...
Page 2: Functional Description
One cycle is required with chip enables asserted to reactivate the outputs. The CY7C0430BV and CY7C0430CV (64K × 18 device) supports burst contains for simple array partitioning. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications.
Page 3 MRST CLKBIST Port 1 Port 1 64K × 18 QuadPort DSE Array Port 2 Port 2 Logic Blocks CY7C0430BV CY7C0430CV Reset Logic JTAG Controller BIST Port 4 Logic Blocks Port 4 Port 3 Port 3 Logic Blocks Page 3 of 37...
Page 4 Port-1 Control Addr. Read Port 1 Readback Register Port 1 Mask Register Port 1 Address Port 1 Decode Counter/ Address Register Port 1 Interrupt Logic MRST CY7C0430BV CY7C0430CV 64K × 18 QuadPort DSE Array Page 4 of 37 [+] Feedback...
Page 5: Pin Configuration
VSS2 VSS2 I/O0 I/O0 VSS2 I/O8 I/O4 I/O2 MRST CLKBIST I/O2 I/O4 1/O7 I/O5 I/O3 I/O1 I/O1 I/O3 I/O5 CY7C0430BV CY7C0430CV I/O16 I/O9 I/O11 I/O13 I/O15 I/O17 I/O17 I/O10 I/O12 I/O14 I/O16 VDD1 VSS2 I/O15 VSS2 VSS2 VDD2 VSS1 CNTRD...
Page 6: Selection Guide
CNTRST CNTRST MKLD MKLD MKLD CNTLD CNTLD CNTLD CNTINC CNTINC CNTINC Document #: 38-06027 Rev. *B CY7C0430CV Port 4 –A –A Address Input/Output. 15P3 15P4 –I/O –I/O Data Bus Input/Output. 17P3 17P4 Clock Input. This input can be free running or strobed.
Page 7 Power Input. Address Lines Ground Input. Address Lines Power Input. Data Lines Ground Input. Data Lines Power Input. CY7C0430BV CY7C0430CV Description = LOW, CE = HIGH), the data lines from the rising = HIGH), the data lines (I/Os) will from the rising edge of the...
Page 8: Maximum Ratings
= 4.0 mA GND ≤ V ≤ V Test Conditions ° = 25 C, f = 1 MHz, = 3.3V CY7C0430BV CY7C0430CV Ambient Temperature ° ° 3.3V ± 150 mV C to +70 ° ° 3.3V ± 150 mV –40 C to +85 –100...
Page 9 Document #: 38-06027 Rev. *B = 50Ω R = 50Ω OUTPUT 5 pF = 50Ω R = 50Ω OUTPUT 5 pF (b) Three-State Delay 3.0V All Input Pulses CY7C0430BV CY7C0430CV = 1.5V = 3.3V Page 9 of 37 [+] Feedback...
Page 10 Min. for commercial is 7.4 ns. MAX2 CYC2 8. This parameter is guaranteed by design, but it is not production tested. 9. Valid for both address and data outputs. Document #: 38-06027 Rev. *B CY7C0430BV and CY7C0430CV –133 –100 Min. Max. Min.
Page 11 TDOV TCK Clock Low to TDO Invalid TDOX Maximum CLKBIST Frequency BIST CLKBIST High Time CLKBIST Low Time Document #: 38-06027 Rev. *B CY7C0430BV CY7C0430CV CY7C0430BV and CY7C0430CV –133 –100 Min. Max. Min. Max. Quadport DSE Family –133/–100 Min. Max.
Page 12: Switching Waveforms
11. To Reset the test port without resetting the device, TMS must be held low for five clock cycles. Document #: 38-06027 Rev. *B TMSH TMSS TDIS TDIH TDOX TDOV CYC2 ACTIVE CY7C0430BV CY7C0430CV TCYC Page 12 of 37 [+] Feedback...
Page 13 15. Addresses do not have to be accessed sequentially. Note 13 indicates that address is constantly loaded on the rising edge of the CLK. Numbers are for reference only. 16. CE is internal signal. CE = VIL if CE and CE Document #: 38-06027 Rev. *B CKLZ following the next rising edge of the clock. CY7C0430BV CY7C0430CV Page 13 of 37 [+] Feedback...
Page 14 22. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06027 Rev. *B CKLZ CKHZ Read No Operation constantly loads the address on the rising edge of the CLK; numbers are for reference only. CY7C0430BV CY7C0430CV CKHZ CKHZ CKLZ CKHZ CKLZ CKLZ Write...
Page 15 24. The “Internal Address” is equal to the “External Address” when CNTLD = V Document #: 38-06027 Rev. *B [19, 20, 21, 22] Read Write [23, 24] SCINC HCINC Counter Hold Read with Counter CY7C0430BV CY7C0430CV CKLZ Read Read with Counter Page 15 of 37 [+] Feedback...
Page 16 = LB = UB = R/W = V ; CE = CNTRST = MRST = MKLD = MKRD = CNTRD = V Document #: 38-06027 Rev. *B [24, 25] Write with Write Counter Counter Hold CY7C0430BV CY7C0430CV Write with Counter Page 16 of 37 [+] Feedback...
Page 17 27. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document #: 38-06027 Rev. *B Write Read Address 0 Address 0 Address 1 CY7C0430BV CY7C0430CV HCLD SCLD Read Read Address n Page 17 of 37 [+] Feedback...
Page 18 31. This is the value of the address counter being read out on the address lines. Document #: 38-06027 Rev. *B HCINC SCRD Read Data with Counter in next clock cycle. CKLZ CKHZ CY7C0430BV CY7C0430CV Note 29 Note 30 CKHZ CKLZ [31] HCRD CKLZ CKHZ...
Page 19 33. This is the value of the Mask Register read out on the address lines. Document #: 38-06027 Rev. *B Note 29 CKLZ SMRD HMRD Read Mask Register Value CY7C0430BV CY7C0430CV Note 30 CKHZ [33] Page 19 of 37 [+] Feedback...
Page 20 > minimum specified value, then Port 2 will read the most recent data (written by Port 1) (t Document #: 38-06027 Rev. *B CKLZ CYC2 CY7C0430BV CY7C0430CV is violated, indeterminate ) after the rising edge of Port 2’s clock. If CYC2 ) after the rising edge of Port 2’s clock.
Page 21 44. Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock. Document #: 38-06027 Rev. *B HCLD HCINC SCINC xx7Dh xx7Eh SINT RINT FFFE CY7C0430BV CY7C0430CV xx7Fh xx00h xx00h SCINT RCINT Page 21 of 37 [+] Feedback...
Page 22 Load Load of Address Lines into Counter/Address Register Increment Counter Increment Readback Readback Counter on Address Lines Readback Readback Mask Register on Address Lines Hold Counter Hold CY7C0430BV CY7C0430CV Operation Deselected Deselected Write Read Outputs Disabled [45, 48, 49] Operation...
Page 23 FFFE FFFD FFFD FFFC FFFC = LBI = UBI = R/WI = MKLDI = MKRDI = CNTRDI = CNTRSTI = CNTLDI = CY7C0430BV CY7C0430CV flag, a write by LOW. A read HIGH. When one Port 3 Port 4 0P4–15P4 FFFF...
Page 24 Table 2. Counter read has a higher priority than mask read. Readback Register Addr. Readback Mask Register Counter/ Address Register CY7C0430BV CY7C0430CV ). When the address readback from the Memory Array Page 24 of 37 [+] Feedback...
Page 25 2. Increment: Once the address counter is loaded with an external address, the counter can internally increment the address value by asserting CNTINC LOW. The counter can CY7C0430BV CY7C0430CV Mask Register bit-0 Address Counter...
Page 26 IEEE 1149.1 Serial Boundary Scan (JTAG) and Memory Built-In-Self-Test (MBIST) The CY7C0430BV and CY7C0430CV incorporate a serial boundary scan test access port (TAP). This port is fully compatible with IEEE Standard 1149.1-2001 operates using JEDEC standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard.
Page 27 Control Register (MCR) is loaded with the default value “00”, loaded into and the TAP controller’s finite state machine (FSM), which is synchronous to TCK, transitions to Run Test/Idle state. The entire MBIST test will be performed with a deterministic CY7C0430BV CY7C0430CV Page 27 of 37 [+] Feedback...
Page 28 Input only and output only signals have an extra dummy cell (odd cells) that are used to ease device layout. P3_IO(17-9) P2_IO(17-9) P3_IO(8-0) P2_IO(8-0) Figure 3. MBIST Debug Register Packet CY7C0430BV CY7C0430CV P1_IO(17-9) P1_IO(8-0) Page 28 of 37 [+] Feedback...
Page 29 53. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-06027 Rev. *B [53] SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR CY7C0430BV CY7C0430CV SELECT IR-SCAN CAPTURE-IR SHIFT-IR EXIT1-IR PAUSE-IR EXIT2-IR UPDATE-IR Page 29 of 37 [+] Feedback...
Page 30 Boundary Scan Register (BSR) CONTROLLER Value Reserved for version number Defines Cypress part number Allows unique identification of QuadPort DSE device vendor Indicate the presence of an ID register CY7C0430BV CY7C0430CV Selection Circuitry (MUX) MRST Description Page 30 of 37 [+] Feedback...
Page 31 Port 1 write all zeros to memory using March2 Algorithm (M2A). Up count M2A_r0w1r1. Up count M2A_r1w0r0. Down count M2A_r0w1r1. Down count M2A_r1w0r0. Read all 0s. Port 1 writes topological checkerboard data to memory. CY7C0430BV CY7C0430CV Bit Size Page 31 of 37 [+] Feedback...
Page 32 All ports read UAA data. Port 4 writes all ones to memory. Port 4 writes inverse address value into memory. All ports read inverse UAA data. Test complete. Mode Debug Reserved Reserved CY7C0430BV CY7C0430CV Description Page 32 of 37 [+] Feedback...
Page 33 UB_P3 OE_P3 R/W_P3 CE1_P3 CE0_P3 INT_P3 CLK_P3 IO0_P4 IO1_P4 IO2_P4 IO3_P4 IO4_P4 IO5_P4 IO6_P4 IO7_P4 IO8_P4 IO0_P3 IO1_P3 IO2_P3 IO3_P3 IO4_P3 IO5_P3 IO6_P3 IO7_P3 IO8_P3 IO0_P1 IO1_P1 CY7C0430BV CY7C0430CV Signal Name Bump (Ball) ID Page 33 of 37 [+] Feedback...
Page 34 A8_P1 A9_P1 A10_P1 A11_P1 A12_P1 A13_P1 A14_P1 A15_P1 CNTINT_P1 CNTRST_P1 MKLD_P1 CNTLD_P1 CNTINC_P1 CNTRD_P1 MKRD_P1 LB_P1 UB_P1 OE_P1 R/W_P1 CE1_P1 CE0_P1 INT_P1 CLK_P1 IO9_P2 IO10_P2 IO11_P2 IO12_P2 CY7C0430BV CY7C0430CV Signal Name Bump (Ball) ID Page 34 of 37 [+] Feedback...
Page 35: Ordering Information
IO15_P4 IO16_P4 IO17_P4 Ordering Information 10 Gb/s 3.3V QuadPort DSE Family 1 Mb (64K × 18) Speed (MHz) Ordering Code CY7C0430BV-133BGI CY7C0430CV-133BGI CY7C0430BV-100BGC CY7C0430BV-100BGI Document #: 38-06027 Rev. *B Bump (Ball) ID Package Name Package Type BG272 272-ball Grid Array (BGA)
Page 36: Package Diagram
The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C0430BV CY7C0430CV 51-85130-*A Page 36 of 37...
Page 37 Document History Page Document Title: CY7C0430BV, CY7C0430CV 10 Gb/s 3.3V QuadPort DSE Family Document Number: 38-06027 Issue Orig. of REV. ECN NO. Date Change 109906 09/10/01 115042 05/23/02 464083 SEE ECN Document #: 38-06027 Rev. *B Description of Change Change from Spec number: 38-01052 to 38-06027...

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Cy7c0430bv

Cypress Semiconductor CY7C0430CV Specification Sheet

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Summary of Contents for Cypress Semiconductor CY7C0430CV

Page 2: Functional Description

Page 5: Pin Configuration

Page 6: Selection Guide

Page 8: Maximum Ratings

Page 12: Switching Waveforms

Page 35: Ordering Information

Page 36: Package Diagram

This manual is also suitable for:

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