Cypress Semiconductor CY7C1336H Specification Sheet

Features
• 64K x 32 common I/O
• 3.3V core power supply
• 3.3V I/O supply
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 8.0 ns (100-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V I/O level
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• "ZZ" Sleep Mode option
Logic Block Diagram
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
D
BW
C
BW
B
BW
A
BWE
GW
CE1
CE2
CE3
OE
SLEEP
ZZ
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-00210 Rev. *A
PRELIMINARY
2-Mbit (64K x 32) Flow-Through Sync SRAM
®
ADDRESS
REGISTER
A
[1:0]
Q1
BURST
COUNTER
AND LOGIC
Q0
CLR
DQ
D
BYTE BYTE
WRITE REGISTER WRITE REGISTER
DQ
C
BYTE
WRITE REGISTER
DQ
B
BYTE
WRITE REGISTER
DQ
A
BYTE
WRITE REGISTER
ENABLE
REGISTER
• 198 Champion Court
Functional Description
The CY7C1336H is a 64K x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE ), depth-expansion Chip Enables (CE
1
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW , and BWE), and Global Write (GW). Asynchronous
[A:D]
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1336H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1336H operates from a +3.3V core power supply
while all outputs may operate with a +3.3V supply. All inputs
and outputs are JEDEC-standard JESD8-5-compatible.
DQ
D
BYTE
WRITE REGISTER
DQ
C
BYTE
WRITE REGISTER
MEMORY
ARRAY
DQ
B
BYTE
WRITE REGISTER
DQ
A
BYTE
WRITE REGISTER
,
• San Jose CA 95134-1709
CY7C1336H
[1]
and CE ), Burst
2 3
OUTPUT
DQs
SENSE
BUFFERS
AMPS
INPUT
REGISTERS
• 408-943-2600
Revised February 6, 2006
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