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Cypress Semiconductor EZ-Host CY7C67300 Specification Sheet

Programmable embedded usb host and peripheral controller with automotive aec grade support
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EZ-Host Features
■
Single chip programmable USB dual-role (Host/Peripheral)
controller with two configurable Serial Interface Engines (SIEs)
and four USB ports
■
Support for USB On-The-Go (OTG) protocol
■
On-chip 48 MHz 16-bit processor with dynamically switchable
clock speed
■
Configurable IO block supporting a variety of IO options or up
to 32 bits of General Purpose IO (GPIO)
■
4K x 16 internal masked ROM containing built in BIOS that
supports a communication ready state with access to I
EEPROM Interface, external ROM, UART, or USB
■
8K x 16 internal RAM for code and data buffering
■
Extended memory interface port for external SRAM and ROM
■
16-bit parallel Host Port Interface (HPI) with a DMA/mailbox
data path for an external processor to directly access all of the
on-chip memory and control on-chip SIEs
■
Fast serial port supports from 9600 baud to 2.0M baud
■
SPI support in both master and slave
CY7C67300 Block Diagram
nRESET
Vbus, ID
D+,D-
D+,D-
Host/
Peripheral
USB Ports
D+,D-
D+,D-
X1
X2
Cypress Semiconductor Corporation
Document #: 38-08015 Rev. *J
EZ-Host™ Programmable Embedded USB Host and
Peripheral Controller with Automotive AEC Grade Support
2
C™
CY7C67300
Timer 0
Control
Watchdog
16-bit RISC CORE
OTG
USB-A
SIE1
USB-B
USB-A
4Kx16
ROM BIOS
SIE2
USB-B
External MEM I/F
Mobile
PLL
Power
Booster
•
198 Champion Court
■
On-chip 16-bit DMA/mailbox data path interface
■
Supports 12 MHz external crystal or clock
■
3.3V operation
■
Automotive AEC grade option (–40°C to 85°C)
■
Package option—100-pin TQFP

Typical Applications

EZ-Host is a very powerful and flexible dual role USB controller
that supports a wide variety of applications. It is primarily
intended to enable host capability in applications such as:
■
Set top boxes
■
Printers
■
KVM switches
■
Kiosks
■
Automotive applications
■
Wireless access points
Timer 1
UART I/F
EEPROM I/F
CY16
HSS I/F
SPI I/F
IDE I/F
8Kx16
RAM
HPI I/F
(SRAM/ROM)
SHARED INPUT/OUTPUT PINS
A[15:0] D[15:0] CTRL[9:0]
,
•
San Jose
CA 95134-1709
CY7C67300
I2C
PWM
GPIO [31:0]
GPIO
•
408-943-2600
Revised July 28, 2008
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Summary of Contents for Cypress Semiconductor EZ-Host CY7C67300

  • Page 1: Typical Applications

    EZ-Host Features ■ Single chip programmable USB dual-role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) and four USB ports ■ Support for USB On-The-Go (OTG) protocol ■ On-chip 48 MHz 16-bit processor with dynamically switchable clock speed ■ Configurable IO block supporting a variety of IO options or up to 32 bits of General Purpose IO (GPIO) ■...

  • Page 2: Functional Overview

    Introduction EZ-Host™ (CY7C67300) is Cypress Semiconductor’s first full-speed, low cost multiport host/peripheral controller. EZ-Host is designed to easily interface to most high performance CPUs to add USB host functionality. EZ-Host has its own 16-bit RISC processor to act as a coprocessor or operate in standalone mode.
  • Page 3 Table 1. Interface Options for GPIO Pins (continued) GPIO Pins GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Table 2. Interface Options for External Memory Bus Pins MEM Pins D[7:0] A[18:0] CONTROL USB Interface EZ-Host has two built in Host/Peripheral SIEs and four USB transceivers that meet the USB 2.0 specification requirements for full and low speed (high speed is not supported).
  • Page 4 Table 3. USB Port Configuration Options (continued) Port Configurations 2 Hosts + 1 Peripheral 2 Hosts + 1 Peripheral 2 Hosts + 1 Peripheral 2 Hosts + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral...
  • Page 5 External Memory Interface EZ-Host provides a robust interface to a wide variety of external memory arrays. All available external memory array locations can contain either code or data. The CY16 RISC processor directly addresses a flat memory space from 0x0000 to 0xFFFF. External Memory Interface Features ■...
  • Page 6 External Memory Interface Pins Table 6. External Memory Interface Pins Pin Name Pin Number nXMEMSEL (optional nCS) nXROMSEL (ROM nCS) nXRAMSEL (RAM nCS) nBEL/A0 nBEH Document #: 38-08015 Rev. *J Table 6. External Memory Interface Pins (continued) Pin Name External Memory Interface Block Diagrams Figure 2 illustrates how to connect a 64k ×...
  • Page 7 Figure 4 illustrates the interface for connecting an 8-bit ROM or 8-bit RAM to the EZ-Host external memory interface. In 8-bit mode, up to 512K bytes of external ROM or RAM are supported. Figure 4. Interfacing up to 512k × 8 for External Code/Data Up to 512k x 8 External Code/Data (Page Mode) EZ-Host External Memory Array...
  • Page 8 SPI Pins The SPI port has a few different pin location options as shown in Table 9. The port location is selectable via the GPIO control register [0xC006]. Table 9. SPI Interface Pins Pin Name Pin Number Default Location nSSI MOSI MISO Alternate Location...
  • Page 9 Host Port Interface EZ-Host has an HPI interface. The HPI interface provides DMA access to the EZ-Host internal memory by an external host, plus a bidirectional mailbox register for supporting high level commu- nication protocols. This port is designed to be the primary high-speed connection to a host processor.
  • Page 10 Table 14. IDE Throughput ATA/ATAPI-4 Mode Min Cycle Time PIO Mode 0 600 ns PIO Mode 1 383 ns PIO Mode 2 PIO Mode 3 180 ns PIO Mode 4 120 ns T = System clock period = 1/48 MHz. IDE Features ■...
  • Page 11 Booster Interface EZ-Host has an on chip power booster circuit for use with power supplies that range between 2.7V and 3.6V. The booster circuit boosts the power to 3.3V nominal to supply power for the entire chip. The booster circuit requires an external inductor, diode, and capacitor.
  • Page 12 Boot Configuration Interface EZ-Host can boot into any one of four modes. The mode it boots into is determined by the TTL voltage level of GPIO[31:30] at the time nRESET is deasserted. Table 19 shows the different boot pin combinations possible. After a reset pin event occurs, the BIOS bootup procedure executes for up to 3 ms.
  • Page 13 Minimum Hardware Requirements for Standalone Mode – Peripheral Only Figure 9. Minimum Standalone Hardware Configuration – Peripheral Only VBus Standard-B or Mini-B SHIELD Up to 64k x8 EEPROM *Bootloading begins after POR + 3ms BIOS bootup *GPIO[31:30] Up to 2k x8 SCL SDA >2k x8 to 64k x8 SDA SCL...

  • Page 14: Memory Map

    External (Remote) Wakeup Source There are several possible events available to wake EZ-Host from Sleep mode as shown in Table 20. These may also be used as remote wakeup options for USB applications. See the Control Register [0xC00A] [R/W] on page 19 Upon wakeup, code begins executing within 200 µs, the time it takes the PLL to stabilize.

  • Page 15: Internal Memory

    Internal Memory HW INT's 0x0000 - 0x00FF SW INT's Primary Registers 0x0100 - 0x011F 0x0120 - 0x013F Swap Registers HPI Int / Mailbox 0x0140 - 0x0148 0x014A - 0x01FF LCP Variables 0x0200 - 0x02FF USB Registers 0x0300 - 0x030F Slave Setup Packet 0x0310 - 0x03FF BIOS Stack 0x0400 - 0x04A2...
  • Page 16 Registers Some registers have different functions for a read vs. a write access or USB host vs. USB device mode. Therefore, registers of this type have multiple definitions for the same address. The default register values listed in this data sheet may be altered to some other value during the BIOS initialization.
  • Page 17 Bank Register [0xC002] [R/W] Table 23. Bank Register Bit # Field Read/Write Default Bit # Field ...Address Read/Write Default Register Description The Bank register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registers R0–R15.
  • Page 18 CPU Speed Register [0xC008] [R/W] Table 26. CPU Speed Register Bit # Field Read/Write Default Bit # Field ...Reserved Read/Write Default Register Description The CPU Speed register allows the processor to operate at a user selected speed. This register only affects the CPU, all other peripheral timing is still based on the 48 MHz system clock (unless otherwise noted).
  • Page 19 Power Control Register [0xC00A] [R/W] Table 28. Power Control Register Bit # Host/Device Host/Device Wake Wake Field Enable Enable Read/Write Default Bit # Reserved Wake Field Enable Read/Write Default Register Description The Power Control register controls the power down and wakeup options.
  • Page 20 Boost 3V OK (Bit 2) The Boost 3V OK bit is a read only bit that returns the status of the OTG Boost circuit. 1: Boost circuit not ok and internal voltage rails are below 3.0V 0: Boost circuit ok and internal voltage rails are at or above 3.0V Sleep Enable (Bit 1) Setting this bit to ‘1’...
  • Page 21 HSS Interrupt Enable (Bit 7) The HSS Interrupt Enable bit enables or disables the following High-speed Serial Interface hardware interrupts: HSS Block Done and HSS RX Full. 1: Enable HSS interrupt 0: Disable HSS interrupt In Mailbox Interrupt Enable (Bit 6) The In Mailbox Interrupt Enable bit enables or disables the HPI: Incoming Mailbox hardware interrupt.
  • Page 22 USB Diagnostic Register [0xC03C] [R/W] Table 31. USB Diagnostic Register Bit # Port 2B Port 2A Diagnostic Diagnostic Field Enable Enable Read/Write Default Bit # ...Reserved Pull-down Field Enable Read/Write Default Register Description The USB Diagnostic register provides control of diagnostic modes.
  • Page 23 Memory Diagnostic Register [0xC03E] [W] Table 33. Memory Diagnostic Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The Memory Diagnostic register provides control of diagnostic modes. Memory Arbitration Select (Bits[10:8]) The Memory Arbitration Select field is defined in Table 34.
  • Page 24 Extended Page n Map Register [R/W] ■ Extended Page 1 Map Register 0xC018 ■ Extended Page 2 Map Register 0xC01A Table 36. Extended Page n Map Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The Extended Page n Map register contains the Page n high-order address bits.
  • Page 25 External Memory Control Register [0xC03A] [R/W] Table 38. External Memory Control Register Bit # Reserved Field Read/Write Default Bit # XROM Width Field Select Read/Write Default Register Description The External Memory Control register provides control of Wait States for the external SRAM or ROM. All wait states are based off of 48 MHz.
  • Page 26 Watchdog Timer Register [0xC00C] [R/W] Table 40. Watchdog Timer Register Bit # Field Read/Write Default Bit # ...Reserved Field Read/Write Default Register Description The Watchdog Timer register provides status and control over the Watchdog timer. The Watchdog timer can also interrupt the processor.
  • Page 27 Timer n Register [R/W] ■ Timer 0 Register 0xC010 ■ Timer 1 Register 0xC012 Table 42. Timer n Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The Timer n Register sets the Timer n count. Both Timer 0 and Timer 1 decrement by one every 1 µs clock tick.
  • Page 28 Port B D– Status (Bit 14) The Port B D– Status bit is a read only bit that indicates the value of DATA– on Port B. 1: D– is HIGH 0: D– is LOW Port A D+ Status (Bit 13) The Port A D+ Status bit is a read only bit that indicates the value of DATA+ on Port A.
  • Page 29 Port A SOF/EOP Enable (Bit 0) The Port A SOF/EOP Enable bit is only applicable in host mode. In device mode this bit must be written as ‘0’. In host mode this bit enables or disables SOFs or EOPs for Port A. Either SOFs or EOPs are generated depending on the LOA bit in the USB n Control register when Port A is active.
  • Page 30 Sequence Select (Bit 6) The Sequence Select bit sets the data toggle for the next packet. This bit has no effect on receiving data packets; sequence checking must be handled in firmware. 1: Send DATA1 0: Send DATA0 Sync Enable (Bit 5) The Sync Enable bit synchronizes the transfer with the SOF packet in full-speed mode and the EOP packet in low-speed mode.
  • Page 31 Register Description The Host n Count register is used to hold the number of bytes (packet length) for the current transaction. The maximum packet length is 1023 bytes in ISO mode. The Host Count value is used to determine how many bytes to transmit, or the maximum number of bytes to receive.
  • Page 32 Sequence Status (Bit 3) The Sequence Status bit indicates the state of the last received data toggle from the device. Firmware is responsible for monitoring and handling the sequence status. The Sequence bit is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to ‘0’...
  • Page 33 Register Description The Host n PID register is a write only register that provides the PID and Endpoint information to the USB SIE to be used in the next transaction. PID Select (Bits [7:4]) The PID Select field is defined in Table 54.
  • Page 34 Host n Device Address Register [W] ■ Host 1 Device Address Register 0xC088 ■ Host 2 Device Address Register 0xC0A8 Table 56. Host n Device Address Register Bit # Field Read/Write Default Bit # Field ...Reserved Read/Write Default Register Description The Host n Device Address register is a write only register that contains the USB Device Address that the host wants to commu- nicate with.
  • Page 35 SOF/EOP Interrupt Enable (Bit 9) The SOF/EOP Interrupt Enable bit enables or disables the SOF/EOP timer interrupt 1: Enable SOF/EOP timer interrupt 0: Disable SOF/EOP timer interrupt Port B Wake Interrupt Enable (Bit 7) The Port B Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port B 1: Enable remote wakeup interrupt for Port B 0: Disable remote wakeup interrupt for Port B...
  • Page 36 SOF/EOP Interrupt Flag (Bit 9) The SOF/EOP Interrupt Flag bit indicates the status of the SOF/EOP Timer interrupt. This bit triggers ‘1’ when the SOF/EOP timer expires. 1: Interrupt triggered 0: Interrupt did not trigger Port B Wake Interrupt Flag (Bit 7) The Port B Wake Interrupt Flag bit indicates remote wakeup on PortB.
  • Page 37 Host n SOF/EOP Counter Register [R] ■ Host 1 SOF/EOP Counter Register 0xC094 ■ Host 2 SOF/EOP Counter Register 0xC0B4 Table 60. Host n SOF/EOP Counter Register Bit # Field Reserved Read/Write Default Bit # Field Read/Write Default Register Description The Host n SOF/EOP Counter register contains the current value of the SOF/EOP down counter.
  • Page 38 USB Device Only Registers There are eleven sets of USB Device Only registers. All sets consist of at least two registers, one for Device Port 1 and one for Device Port 2. In addition, each Device port has eight possible endpoints. This gives each endpoint register set eight registers for each Device Port for a total of sixteen registers per set.
  • Page 39 Sequence Select (Bit 6) The Sequence Select bit determines whether a DATA0 or a DATA1 is sent for the next data toggle. This bit has no effect on receiving data packets; sequence checking must be handled in firmware. 1: Send a DATA1 0: Send a DATA0 Stall Enable (Bit 5) The Stall Enable bit sends a Stall in response to the next request...
  • Page 40 Register Description The Device n Endpoint n Address register is used as the base pointer into memory space for the current Endpoint transaction. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Address register.
  • Page 41 Device n Endpoint n Status Register [R/W] ■ Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286] ■ Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296] ■ Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6] ■...
  • Page 42 underflow and the Overflow and Underflow flags (bits 11 and 10 respectively) must be checked to determine which event occurred. 1: An overflow or underflow condition occurred 0: An overflow or underflow condition did not occur Setup Flag (Bit 4) The Setup Flag bit indicates that a setup packet was received.
  • Page 43 The Device n Endpoint n Count Result register is a memory-based register that must be initialized to 0x0000 before USB Device operations are initiated. After initialization, do not write to this register again. Result (Bits [15:0]) The Result field contains the differences in bytes between the received packet and the value specified in the Device n Endpoint n Count register.
  • Page 44 supported in Port 1A). This bit is only available for Device 1 and is a reserved bit in Device 2. 1: Enable VBUS interrupt 0: Disable VBUS interrupt ID Interrupt Enable (Bit 14) The ID Interrupt Enable bit enables or disables the OTG ID interrupt.
  • Page 45 Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt. 1: Enable EP1 Transaction Done interrupt 0: Disable EP1 Transaction Done interrupt EP0 Interrupt Enable (Bit 0) The EP0 Interrupt Enable bit enables or disables endpoint zero (EP0) Transaction Done interrupt.
  • Page 46 Register Description The Device n Status register provides status information for device operation. Pending interrupts can be cleared by writing a ‘1’ to the corresponding bit. This register can be accessed by the HPI interface. VBUS Interrupt Flag (Bit 15) The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A).
  • Page 47 EP2 Interrupt Flag (Bit 2) The EP2 Interrupt Flag bit indicates if the endpoint two (EP2) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error.
  • Page 48 Device n SOF/EOP Count Register [W] ■ Device 1 SOF/EOP Count Register 0xC094 ■ Device 2 SOF/EOP Count Register 0xC0B4 Table 73. Device n SOF/EOP Count Register Bit # Field Reserved Read/Write Default Bit # Field Read/Write Default Register Description The Device n SOF/EOP Count register is written with the time expected between receiving a SOF/EOP.
  • Page 49 Receive Disable (Bit 12) The Receive Disable bit enables or powers down (disables) the OTG receiver section. 1: OTG receiver powered down and disabled 0: OTG receiver enabled Charge Pump Enable (Bit 11) The Charge Pump Enable bit enables or disables the OTG VBus charge pump.
  • Page 50 GPIO Control Register [0xC006] [R/W] Table 77. GPIO Control Register Bit # Write Protect Field Enable Read/Write Default Bit # HSS XD Field Enable Enable Read/Write Default Register Description The GPIO Control register configures the GPIO pins for various interface options. It also controls the polarity of the GPIO interrupt on IRQ1 (GPIO25) and IRQ0 (GPIO24).
  • Page 51 Interrupt 0 Polarity Select (Bit 1) The Interrupt 0 Polarity Select bit selects the polarity for IRQ0. 1: Sets IRQ0 to rising edge 0: Sets IRQ0 to falling edge Interrupt 0 Enable (Bit 0) The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO bit on the interrupt Enable register must also be set in order for this for this interrupt to be enabled.
  • Page 52 GPIO n Direction Register [R/W] ■ GPIO 0 Direction Register 0xC022 ■ GPIO 1 Direction Register 0xC028 Table 81. GPIO n Direction Register Bit # 31/15 30/14 Field Read/Write Default Bit # 23/7 22/6 Field Read/Write Default Register Description The GPIO n Direction register controls the direction of the GPIO data pins (input/output).
  • Page 53 Table 84. Mode Select Definition Mode Select [2:0] Reserved Write all reserved bits with ’0’. IDE Start Address Register [0xC04A] [R/W] Table 85. IDE Start Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The IDE Start Address register holds the start address for an IDE block transfer.
  • Page 54 IDE Stop Address Register [0xC04C] [R/W] Table 86. IDE Stop Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The IDE Stop Address register holds the stop address for an IDE block transfer. This register is byte addressed and IDE block transfers are 16-bit words, therefore the LSB of the stop address is ignored.
  • Page 55 IDE PIO Port Registers [0xC050 - 0xC06F] [R/W] All IDE PIO Port registers [0xC050 - 0xC06F] in Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. The table Address column denotes the CY7C67300 register address for the corresponding ATA/ATAPI register. The IDE_nCS[1:0] field defines the ATA interface CS addressing bits and the IDE_A[2:0] field define the ATA interface address bits.
  • Page 56 HSS Control Register [0xC070] [R/W] Table 90. HSS Control Register Bit # Enable Polarity Field Select Read/Write Default Bit # Transmit Receive Done Interrupt Done Interrupt Field Enable Enable Read/Write Default Register Description The HSS Control register provides high level status and control over the HSS port.
  • Page 57 Transmit Ready (Bit 4) The Transmit Ready bit is a read only bit that indicates if the HSS Transmit FIFO is ready for the CPU to load new data for trans- mission. 1: HSS transmit FIFO ready for loading 0: HSS transmit FIFO not ready for loading Packet Mode Select (Bit 3) The Packet Mode Select bit selects between Receive Packet Ready and Receive Ready as the interrupt source for the RxIntr...
  • Page 58 HSS Transmit Gap Register [0xC074] [R/W] Table 92. HSS Transmit Gap Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The HSS Transmit Gap register is only valid in block transmit mode. It allows for a programmable number of stop bits to be inserted, thus overwriting the One Stop Bit in the HSS Control register.
  • Page 59 HSS Receive Address Register [0xC078] [R/W] Table 94. HSS Receive Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The HSS Receive Address register is used as the base pointer address for the next HSS block receive transfer. HSS Receive Counter Register [0xC07A] [R/W] Table 95.
  • Page 60 HSS Transmit Address Register [0xC07C] [R/W] Table 96. HSS Transmit Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The HSS Transmit Address register is used as the base pointer address for the next HSS block transmit transfer. HSS Transmit Counter Register [0xC07E] [R/W] Table 97.
  • Page 61 HPI Registers There are five registers dedicated to HPI operation. In addition, there is an HPI status port which can be addressed over HPI. Each of these registers is covered in this section and are summa- rized in Table HPI Breakpoint Register [0x0140] [R] Table 99.
  • Page 62 ID to HPI Enable (Bit 14) The ID to HPI Enable bit routes the OTG ID interrupt to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port SOF/EOP2 to HPI Enable (Bit 13) The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt to the HPI port.
  • Page 63 SIEXmsg Register [W] ■ SIE1msg Register 0x0144 ■ SIE2msg Register 0x0148 Table 101. SIEXmsg Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The SIEXmsg register allows an interrupt to be generated on the HPI port. Any write to this register causes the SIEXmsg flag in the HPI Status Port to go high and also causes an interrupt on the HPI_INTR pin.
  • Page 64 HPI Status Port [] [HPI: R] Table 103. HPI Status Port Bit # VBUS Field Flag Flag Read/Write Default Bit # Resume2 Resume1 Field Flag Flag Read/Write Default Register Description The HPI Status Port provides the external host processor with the MailBox status bits plus several SIE status bits.
  • Page 65 Done1 Flag (Bit 2) In host mode the Done 1 Flag bit is a read only bit that indicates if a host packet done interrupt occurs on Host 1. In device mode this read only bit indicates if an any of the endpoint interrupts occur on Device 1.
  • Page 66 SPI Configuration Register [0xC0C8] [R/W] Table 105. SPI Configuration Register Bit # 3Wire Phase Field Enable Select Read/Write Default Bit # Master Master Active Enable Field Enable Read/Write Default Register Description The SPI Configuration register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
  • Page 67 SPI Control Register [0xC0CA] [R/W] Table 107. SPI Control Register Bit # FIFO Strobe Init Field Read/Write Default Bit # Transmit Receive Field Empty Full Read/Write Default Register Description The SPI Control register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
  • Page 68 Receive Bit Length (Bits [2:0]) The Receive Bit Length field controls whether a full byte or partial byte is received. If Receive Bit Length is ‘000’ then a full byte is received. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that are received.
  • Page 69 Receive Interrupt Flag (Bit 2) The Receive Interrupt Flag is a read only bit that indicates if a byte mode receive interrupt triggered. 1: Indicates a byte mode receive interrupt triggered 0: Indicates a byte mode receive interrupt did not trigger Transmit Interrupt Flag (Bit 1) The Transmit Interrupt Flag is a read only bit that indicates a byte mode transmit interrupt triggered.
  • Page 70 Table 112. CRC Mode Definition CRCMode CRC Polynomial [15:14] MMC 16 bit: X^16 + X^12 + X^5 + 1(CCITT Standard) CRC7 7 bit: X^7+ X^3 + 1 MST 16 bit: X^16+ X^15 + X^2 + 1 Reserved, 16 bit polynomial 1 CRC Enable (Bit 13) The CRC Enable bit enables or disables the CRC operation.
  • Page 71 SPI Data Register [0xC0D6] [R/W] Table 114. SPI Data Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The SPI Data register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO byte mode.
  • Page 72 SPI Transmit Count Register [0xC0DA] [R/W] Table 116. SPI Transmit Count Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The SPI Transmit Count register designates the block byte length for the SPI transmit DMA transfer. Count (Bits [10:0]) The Count field sets the count for the SPI transmit DMA transfer.
  • Page 73 Register Description The SPI Receive Count register designates the block byte length for the SPI receive DMA transfer. Count (Bits [10:0]) The Count field sets the count for the SPI receive DMA transfer. Reserved Write all reserved bits with ’0’. UART Control Register [0xC0E0] [R/W] Table 120.
  • Page 74 UART Status Register [0xC0E2] [R] Table 122. UART Status Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The UART Status register is a read only register that indicates the status of the UART buffer. Receive Full (Bit 1) The Receive Full bit indicates whether the receive buffer is full.
  • Page 75 PWM Registers There are eleven registers dedicated to PWM operation. Each of these registers are covered in this section and summarized in Table 124. Table 124. PWM Registers Register Name PWM Control Register PWM Maximum Count Register PWM0 Start Register PWM0 Stop Register PWM1 Start Register PWM1 Stop Register...
  • Page 76 Mode Select (Bit 8) The Mode Select bit selects between continuous PWM cycling and one shot mode. The default is continuous repeat. 1: Enable One Shot mode. The mode runs the number of counter cycles set in the PWM Cycle Count register and then stops. 0: Enable Continuous mode.
  • Page 77 PWM n Start Register [R/W] ■ PWM 0 Start Register 0xC0EA ■ PWM 1 Start Register 0xC0EE ■ PWM 2 Start Register 0xC0F2 ■ PWM 3 Start Register 0xC0F6 Table 128. PWM n Start Register Bit # Field Read/Write Default Bit # Field Read/Write...
  • Page 78 PWM Cycle Count Register [0xC0FA] [R/W] Table 130. PWM Cycle Count Register Bit # Field Read/Write Default Bit # Field Read/Write Default Register Description The PWM Cycle Count register designates the number of cycles to run when in one shot mode. One shot mode is enabled by setting the Mode Select bit of the PWM Control register to ‘1’.

  • Page 79: Pin Diagram

    Pin Diagram Figure 11. EZ-Host Pin Diagram 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DM2B DP2B AGND DM2A DP2A OTGVBUS CSWITCHB CSWITCHA VSWITCH BOOSTGND BOOSTVCC...
  • Page 80 Table 131. Pin Descriptions (continued) Name D11/MOSI D10/SCK D9/nSSI D8/MISO nBEL/A0 nBEH nXMEMSEL nXROMSEL nXRAMSEL A15/CLKSEL GPIO31/SCK GPIO30/SDA Document #: 38-08015 Rev. *J Type Description D11: External Memory Data Bus MOSI: SPI MOSI D10: External Memory Data Bus SCK: SPI SCK D9: External Memory Data Bus nSSI: SPI nSSI D8: External Memory Data Bus...
  • Page 81 Table 131. Pin Descriptions (continued) Name GPIO29/OTGID GPIO28/TX GPIO27/RX GPIO26/CTS/PWM3 GPIO25/IRQ1 GPIO24/INT/ IORDY/IRQ0 GPIO23/nRD/IOR GPIO22/nWR/IOW GPIO21/nCS GPIO20/A1/CS1 GPIO19/A0/CS0 GPIO18/A2/RTS/ PWM2 GPIO17/A1/RXD/ PWM1 GPIO16/A0/TXD/ PWM0 GPIO15/D15/nSSI GPIO14/D14 GPIO13/D13 GPIO12/D12 Document #: 38-08015 Rev. *J Type Description GPIO29: General Purpose IO OTGID: Input for OTG ID pin. When used as OTGID, tie this pin high through an external pull up resistor.
  • Page 82 Table 131. Pin Descriptions (continued) Name GPIO11/D11/MOSI GPIO10/D10/SCK GPIO9/D9/nSSI GPIO8/D8/MISO GPIO7/D7 GPIO6/D6 GPIO5/D5 GPIO4/D4 GPIO3/D3 GPIO2/D2 GPIO1/D1 GPIO0/D0 DM1A DP1A DM1B DP1B DM2A DP2A DM2B DP2B XTALIN XTALOUT nRESET Reserved BOOSTV VSWITCH BOOSTGND OTGVBUS CSWITCHA CSWITCHB AGND 37, 63, 88 26, 51, 75, Document #: 38-08015 Rev.

  • Page 83: Absolute Maximum Ratings

    Absolute Maximum Ratings This section lists the absolute maximum ratings. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability. Storage Temperature ... –40°C to +125°C Ambient Temperature with Power Supplied..
  • Page 84 Table 133. DC Characteristics (continued) Parameter Description Sleep Current SLEEP Sleep Current with Booster Enabled USB Peripheral: includes 1.5K SLEEPB Table 134. DC Characteristics: Charge Pump Parameter Description Regulated OTGVBUS Voltage A_VBUS_OUT Rise Time A_VBUS_RISE Maximum Load Current A_VBUS_OUT OUTVBUS Bypass Capacitance DRD_VBUS OTGVBUS Leakage Voltage A_VBUS_LKG...

  • Page 85: Reset Timing

    AC Timing Characteristics Reset Timing nRESET nRD or nWRL or nWRH Table 135. Reset Timing Parameters Parameter Description nRESET Pulse Width RESET nRESET HIGH to nRD or nWRx active IOACT Clock Timing XTALIN HIGH Table 136. Clock Timing Parameters Parameter Description Clock Frequency [12]...
  • Page 86 [15] SRAM Read Cycle Address Table 137. SRAM Read Cycle Parameters Parameter Description CS LOW to RD LOW RD HIGH to Data Hold CS HIGH to Data Hold [13] RD LOW Time RD LOW to Address Valid [14] RAM Access to Data Valid Notes 13.
  • Page 87 [17] SRAM Write Cycle Address Dout Table 138. SRAM Write Cycle Parameters Parameter Description Write Address Valid to WE LOW CS LOW to WE LOW Data Valid to WE HIGH [16] WE Pulse Width Data Hold from WE HIGH WE HIGH to CS HIGH Notes 16.
  • Page 88 I2C EEPROM Timing-Serial IO SU.STA HD.STA SDA IN SDA OUT Table 139. I2C EEPROM Timing Parameters Parameter Description Clock Frequency Clock Pulse Width Low Clock Pulse Width High HIGH Clock Low to Data Out Valid Bus Idle Before New Transmission Start Hold Time HD.STA Start Setup Time...
  • Page 89 HPI (Host Port Interface) Write Cycle Timing ADDR [1:0] CSSU Dout [15:0] Table 140. HPI Write Cycle Timing Parameters Parameter Description Address Setup Address Hold Chip Select Setup CSSU Chip Select Hold Data Setup Write Data Hold Write Pulse Width Write Cycle Time Notes 18.
  • Page 90 HPI (Host Port Interface) Read Cycle Timing ADDR [1:0] CSSU Din [15:0] Table 141. HPI Read Cycle Timing Parameters Parameter Description Address Setup Address Hold Chip Select Setup CSSU Chip Select Hold Data Access Time, from HPI_nRD falling Read Data Hold, relative to the earlier of HPI_nRD rising or HPI_nCS rising Read Pulse Width Read Cycle Time...
  • Page 91 IDE Timing The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment–4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. HSS BYTE Mode Transmit qt_clk CPU_A[2:0] CPUHSS_cs CPU_wr TxRdy flag HSS_TxD Byte transmit triggered by a CPU write to the HSS_TxData register qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate the relationship between CPU opera-...

  • Page 92: Register Summary

    Hardware CTS/RTS Handshake tCTSsetup HSS_RTS HSS_CTS HSS_TxD Start of transmission delayed until HSS_CTS goes high : HSS_CTS setup time before HSS_RTS = 1.5T min. CTSsetup : HSS_CTS hold time after START bit = 0 ns min. CTShold T = 1/48 MHz. When RTS/CTS hardware handshake is enabled, transmission can be help off by deasserting HSS_CTS at least 1.5T before HSS_RTS.
  • Page 93 Table 142. Register Summary (continued) Address Register Bit 15 Bit 7 0xC00C Watchdog Timer Reserved..Reserved 0xC00E Interrupt Enable Reserved Interrupt Enable 0xC098 OTG Control Reserved D+ Pulldown Enable 0: 0xC010 Timer n Count... 1: 0xC012 ...Count 0xC014 Breakpoint Address..Address 1: 0xC018 Extended Page n Map...
  • Page 94 Table 142. Register Summary (continued) Address Register Bit 15 Bit 7 0xC07E HSS Transmit Counter Reserved ...Counter 0xC080 Host n Control Reserved 0xC0A0 Preamble Enable 0xC082 Host n Address Address... 0xC0A2 ...Address 0xC084 Host n Count Reserved 0xC0A4 ...Count 0xC084 Device n Port Select Reserved 0xC0A4...
  • Page 95 Table 142. Register Summary (continued) Address Register Bit 15 Bit 7 0xC0AC Device 2 Interrupt Enable Reserved Interrupt Enable 0xC0B0 Host 2 Status Reserved Port B Wake Interrupt Flag 0xC0B0 Device 2 Status Reserved Interrupt Flag 0xC0C6 HPI Mailbox Message..Message 0xC0C8 SPI Configuration...
  • Page 96 Table 142. Register Summary (continued) Address Register Bit 15 Bit 7 PWM n Stop Reserved 0xC0EC ...Address 1: 0xC0F0 2: 0xC0F4 3: 0xC0F8 0xC0FA PWM Cycle Count Count..Count HPI Status Port VBUS Flag Resume2 Flag Resume1 Flag SIE2msg Document #: 38-08015 Rev. *J Bit 14 Bit 13 Bit 12...

  • Page 97: Ordering Information

    Ordering Information Table 143. Ordering Information Ordering Code CY7C67300-100AXI 100 TQFP CY7C67300-100AXA 100 TQFP CY7C67300-100AXIT 100 TQFP, tape and reel CY7C67300-100AXAT 100 TQFP, tape and reel CY3663 Development Kit Package Diagrams Figure 12. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100SA 16.00±0.25 SQ 14.00±0.05 SQ SEATING PLANE...
  • Page 98 Document History Page Document Title: CY7C67300 EZ-Host™ Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Document Number: 38-08015 Orig. of REV. ECN NO. Change sion Date 111872 116989 125262 126210 127335 129395 443992 566465 KKVTMP 1063560 2514867 PYRS 2544823...
  • Page 99 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless wireless.cypress.com Memories memory.cypress.com...

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