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Features
■
True Dual-Ported memory cells which allow
simultaneous access of the same memory location
■
32K x 16 organization (CY7C027V/027VN/027AV
■
64K x 16 organization (CY7C028V)
■
32K x 18 organization (CY7C037V/037AV
■
64K x 18 organization (CY7C038V)
■
0.35 micron CMOS for optimum speed and power
■
High speed access: 15, 20, and 25 ns
■
Low operating power
■
Active: I
= 115 mA (typical)
CC
= 10 μA (typical)
■
Standby: I
SB3
Logic Block Diagram
R/W
L
UB
L
CE
0L
CE
1L
CE
L
LB
L
OE
L
[3]
I/O
–I/O
8/9L
15/17L
[4]
I/O
–I/O
0L
7/8L
15/16
[5]
A
–A
0L
14/15L
[5]
A
–A
0L
14/15L
CE
L
OE
L
R/W
L
SEM
L
[6]
BUSY
L
INT
L
UB
L
LB
L
Notes
1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical.
2. CY7C037V and CY7C037AV are functionally identical.
3. I/O
–I/O
for x16 devices; I/O
–I/O
8
15
9
4. I/O
–I/O
for x16 devices; I/O
–I/O
0
7
0
5. A
–A
for 32K; A
–A
for 64K devices.
0
14
0
15
6. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06078 Rev. *B
3.3V 32K/64K x 16/18 Dual-Port Static
[1]
)
[2]
)
8/9
8/9
I/O
Control
Address
True Dual-Ported
RAM Array
Decode
15/16
Semaphore
for x18 devices.
17
for x18 devices.
8
•
198 Champion Court
CY7C027V/027VN/027AV/028V
■
Fully asynchronous operation
■
Automatic power down
■
Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
■
On-chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Separate upper-byte and lower-byte control
■
Dual chip enables
■
Pin select for Master or Slave
■
Commercial and Industrial temperature ranges
■
100-pin Pb-free TQFP and 100-pin TQFP
I/O
Control
Address
Decode
15/16
Interrupt
Arbitration
M/S
•
San Jose
CY7C037V/037AV/038V
R/W
R
UB
R
CE
0R
CE
CE
1R
R
LB
R
OE
R
8/9
[3]
I/O
–I/O
8/9L
15/17R
8/9
[4]
I/O
–I/O
0L
7/8R
15/16
[5]
A
–A
0R
14/15R
[5]
A
–A
0R
14/15R
CE
R
OE
R
R/W
R
SEM
R
[6]
BUSY
R
INT
R
UB
R
LB
R
,
CA 95134-1709
•
408-943-2600
Revised December 09, 2008
RAM
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Table of Contents
Related Manuals for Cypress Semiconductor CY7C027AV
Summary of Contents for Cypress Semiconductor CY7C027AV
- Page 1 Address –A 14/15L Decode 15/16 –A 14/15L BUSY Notes 1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical. 2. CY7C037V and CY7C037AV are functionally identical. 3. I/O –I/O for x16 devices; I/O –I/O for x18 devices. 4. I/O –I/O for x16 devices; I/O –I/O...
-
Page 2: Pin Configurations
Pin Configurations A10L A11L A12L A13L A14L A15L CE0L CE1L CY7C027V/027VN/027AV (32K x 16) SEML R/WL I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L Note 1. This pin is NC for CY7C027V/027VN/027AV. Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V Figure 1. 100-Pin TQFP (Top View) 92 91 90 87 86 83 82 81... -
Page 3: Selection Guide
Pin Configurations (continued) A10L A11L A12L A13L A14L A15L CE0L CE1L SEML R/WL I/O17L I/O16L I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L Selection Guide Parameter Maximum Access Time Typical Operating Current Typical Standby Current for I (Both ports TTL level) Typical Standby Current for I (Both ports CMOS level) Note 2. -
Page 4: Pin Definitions
Pin Definitions Left Port Right Port , CE , CE –A –A –I/O –I/O BUSY BUSY Architecture CY7C027V/027VN/027AV/028V CY7037V/037AV/038V consist of an array of 32K and 64K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). - Page 5 generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port.
-
Page 6: Maximum Ratings
Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ... –65 Ambient Temperature with Power Applied ... –55 Supply Voltage to Ground Potential...–0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State ... -
Page 7: Switching Characteristics
3.3V R1 = 590Ω OUTPUT C = 30 pF R2 = 435Ω (a) Normal Load (Load 1) 3.0V Switching Characteristics Over the Operating Range Parameter Description Read Cycle Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid [8, 9, 10]... -
Page 8: Data Retention Mode
Switching Characteristics Over the Operating Range Parameter Description Data Hold From Write End [9, 10] R/W LOW to High Z HZWE [9 ,10] R/W HIGH to Low Z LZWE [36] Write Pulse to Data Delay [36] Write Data Valid to Read Data Valid [11] Busy Timing BUSY LOW from Address Match... -
Page 9: Switching Waveforms
Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access) ADDRESS DATA OUT PREVIOUS DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) CE and LB or UB DATA OUT CURRENT Figure 6. Read Cycle No. 3 (Either Port) ADDRESS UB or LB DATA OUT... - Page 10 Switching Waveforms (continued) Figure 7. Write Cycle No. 1: R/W Controlled Timing ADDRESS [24,25] NOTE 27 DATA OUT DATA IN Figure 8. Write Cycle No. 2: CE Controlled Timing ADDRESS [24,25] DATA IN Notes 20. R/W must be HIGH during all address transitions. 21.
- Page 11 Switching Waveforms (continued) Figure 9. Semaphore Read After Write Timing, Either Side –A VALID ADRESS Figure 10. Timing Diagram of Semaphore Contention –A –A Notes 29. CE = HIGH for the duration of the above timing (both write and read cycle). 30.
- Page 12 Switching Waveforms (continued) Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS DATA IN ADDRESS BUSY DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) BUSY Note 33. CE = CE = LOW. Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V MATCH VALID...
- Page 13 Switching Waveforms (continued) Figure 13. Busy Timing Diagram No. 1 (CE Arbitration) Valid First: ADDRESS BUSY Valid First: ADDRESS BUSY Figure 14. Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: ADDRESS ADDRESS MATCH ADDRESS BUSY Right Address Valid First: ADDRESS ADDRESS MATCH ADDRESS...
- Page 14 Switching Waveforms (continued) Left Side Sets INT ADDRESS WRITE 7FFF (FFFF for CY7C028V/38V) [36] Right Side Clears INT ADDRESS Right Side Sets INT ADDRESS WRITE 7FFE (FFFE for CY7C028V/38V) [36] Left Side Clears INT ADDRESS Notes 35. t depends on which enable pin (CE or R/W ) is deasserted first.
- Page 15 Table 1. Non-Contending Read/Write Inputs Table 2. Interrupt Operation Example (assumes BUSY Function Set Right INT Flag Reset Right INT Flag Set Left INT Flag Reset Left INT Flag Table 3. Semaphore Operation Example Function –I/O No action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore...
-
Page 16: Ordering Information
Ordering Information 32K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code CY7C027V-15AC CY7C027V-15AXC CY7C027VN-15AXC CY7C027V-20AC CY7C027V-20AXC CY7C027V-25AC CY7C027V-25AXC CY7C027AV-25AXI 64K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code CY7C028V-15AC CY7C028V-15AXC CY7C028V-20AC CY7C028V-20AXC CY7C028V-20AI CY7C028V-20AXI CY7C028V-25AC CY7C028V-25AXC 32K x18 3.3V Asynchronous Dual-Port SRAM... -
Page 17: Package Diagram
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-*C Document #: 38-06078 Rev. *B Page 17 of 18 [+] Feedback... - Page 18 Converted data sheet from old spec 38-00670 to conform with new data sheet. Removed cross information from features section See ECN Added Pb-Free packaging information. 12/17/08 Added CY7C027VN, CY7C027AV and CY7C037AV parts Updated Ordering information table PSoC Solutions General psoc.cypress.com Low Power/Low Voltage clocks.cypress.com...
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