Table of Contents
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Features
True dual-ported memory cells that allow simultaneous access
■
of the same memory location
Synchronous pipelined operation
■
Organization of 1-Mbit, 2-Mbit, 4-Mbit, and 9-Mbit devices
■
Pipelined output mode allows fast operation
■
0.18-micron CMOS for optimum speed and power
■
High-speed clock to data access
■
3.3V low power
■
Active as low as 225 mA (typ)
❐
Standby as low as 55 mA (typ)
❐
Mailbox function for message passing
■
Global master reset
■
Separate byte enables on both ports
■
Commercial and industrial temperature ranges
■
IEEE 1149.1-compatible JTAG boundary scan
■
172-Ball FBGA (1 mm pitch) (15 mm × 15 mm)
■
176-Pin TQFP (24 mm × 24 mm × 1.4 mm)
■
Counter wrap around control
■
Internal mask register controls counter wrap-around
❐
Counter-interrupt flags to indicate wrap-around
❐
Memory block retransmit operation
❐
Counter readback on address lines
■
Mask register readback on address lines
■
Dual Chip Enables on both ports for easy depth expansion
■
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
Max. Access Time - Clock to Data (ns)
Typical operating current (mA)
Package
Cypress Semiconductor Corporation
Document #: 38-06070 Rev. *H
FLEx36™ 3.3V 32K/64K/128K/256K x 36
Functional Description
The FLEx36™ family includes 1M, 2M, 4M, and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0853AV device in this family has limited features.
Please see
Operations" on page 8.
1-Mbit
(32K x 36)
CY7C0850AV
167
4.0
225
176TQFP
172FBGA
•
198 Champion Court
CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Synchronous Dual-Port RAM
See "Address Counter and Mask Register
for details.
2-Mbit
4-Mbit
(64K x 36)
(128K x 36)
CY7C0851AV
CY7C0852AV
167
167
4.0
4.0
225
225
176TQFP
176TQFP
172FBGA
172FBGA
,
•
San Jose
CA 95134-1709
9-Mbit
(256K x 36)
CY7C0853AV
133
4.7
270
172FBGA
•
408-943-2600
Revised July 29, 2008
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Table of Contents
Related Manuals for Cypress Semiconductor FLEx36 CY7C0850AV
Summary of Contents for Cypress Semiconductor FLEx36 CY7C0850AV
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Page 1: Functional Description
Features True dual-ported memory cells that allow simultaneous access ■ of the same memory location Synchronous pipelined operation ■ Organization of 1-Mbit, 2-Mbit, 4-Mbit, and 9-Mbit devices ■ Pipelined output mode allows fast operation ■ 0.18-micron CMOS for optimum speed and power ■... -
Page 2: Logic Block Diagram
Logic Block Diagram –DQ –DQ –DQ –DQ Addr. Read Back –A Mask Register CNT/MSK Counter/ Address CNTEN Register CNTRST Mirror Reg CNTINT Interrupt Logic Note 1. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits. Document #: 38-06070 Rev. -
Page 3: Pin Configurations
Pin Configurations DQ32L DQ30L CNTINTL DQ33L DQ29L DQ17L DQ31L DQ27L DQ35L DQ34L CE1L CE0L R/WL CLKL A10L ADSL A11L A12L A15L CNTRSTL CNT/MSKL A13L CNTENL DQ26L A16L A14L DQ22L DQ18L DQ24L DQ20L DQ8L DQ6L DQ23L DQ21L Note 2. For CY7C0851AV, pins M1 and M14 are NC. For CY7C0850AV, pins K3, K12 M1, and M14 are NC Document #: 38-06070 Rev. - Page 4 Pin Configurations (continued) DQ32L DQ30L DQ33L DQ29L A17L DQ31L DQ35L R/WL A10L A11L A12L A15L A13L A16L A14L DQ22L DQ24L DQ20L DQ8L DQ23L DQ21L Document #: 38-06070 Rev. *H Figure 2. 172-Ball BGA (Top View) DQ13L DQ11L DQ11R DQ17L DQ14L DQ12L DQ9L DQ9R...
- Page 5 Pin Configurations (continued) Figure 3. 176-Pin Thin Quad Flat Pack (TQFP) (Top View) CNTEN CNTRST CNT/MSK Document #: 38-06070 Rev. *H CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV MRST CNTEN CNTRST CNT/MSK Page 5 of 32 [+] Feedback...
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Page 6: Pin Definitions
Pin Definitions Left Port Right Port –A –A Address Inputs. Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for the part using the externally supplied address on the address pins and for loading this address into the burst address counter. -
Page 7: Master Reset
Master Reset The FLEx36 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchro- nously to the clocks. The MRST initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). - Page 8 Address Counter and Mask Register Operations [10] This section describes the features only apply to CY7C0850AV/CY7C0851AV/CY7C0852AV devices, but not to the CY7C0853AV device. Each port of these devices has a programmable burst address counter. The burst counter contains three registers: a counter register, a mask register, and a mirror register.
- Page 9 Counter Interrupt The counter interrupt (CNTINT) is asserted LOW when an increment operation results in the unmasked portion of the counter register being all “1s.” It is deasserted HIGH when an Increment operation results in any other value. It is also de-asserted by Counter Reset, Counter Load, Mask Reset and Mask Load operations, and by MRST.
- Page 10 Figure 4. Counter, Mask, and Mirror Logic Block Diagram CNT/MSK CNTEN Decode Logic CNTRST MRST Bidirectional Address Lines From Address Lines From Mask Register From Mask From Counter Document #: 38-06070 Rev. *H Mask Register Counter/ Address Register Load/Increment Mirror Counter Increment Logic...
- Page 11 Figure 5. Programmable Counter-Mask Register Operation CNTINT Example: Load Counter-Mask Register = 3F Load Address Counter = 8 Address Register Max + 1 Address Register Document #: 38-06070 Rev. *H Masked Address Unmasked Address CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [1, 12] Mask Register bit-0...
- Page 12 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV incorporates an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs. JEDEC-standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard.
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Page 13: Maximum Ratings
Maximum Ratings [15] Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ... –65 Ambient Temperature with Power Applied ... –55 Supply Voltage to Ground Potential...–0.5V to + 4.6V DC Voltage Applied to Outputs in High-Z State ... -
Page 14: Switching Characteristics
= 50Ω OUTPUT C = 10 pF (a) Normal Load (Load 1) ALL INPUT PULSES Switching Characteristics Over the Operating Range Parameter Description Maximum Operating Frequency MAX2 Clock Cycle Time CYC2 Clock HIGH Time Clock LOW Time [19] Clock Rise Time [19] Clock Fall Time Address Setup Time... - Page 15 Switching Characteristics Over the Operating Range (continued) Parameter Description Output Enable to Data Valid [20, 21] OE to Low Z [20, 21] OE to High Z Clock to Data Valid Clock to Counter Address Valid Clock to Mask Register Readback Valid Data Output Hold After Clock HIGH [20, 21] Clock HIGH to Output High Z...
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Page 16: Jtag Timing
JTAG Timing Parameter Maximum JTAG TAP Controller Frequency JTAG TCK Clock Cycle Time TCYC TCK Clock HIGH Time TCK Clock LOW Time TMS Setup to TCK Clock Rise TMSS TMS Hold After TCK Clock Rise TMSH TDI Setup to TCK Clock Rise TDIS TDI Hold After TCK Clock Rise TDIH... -
Page 17: Switching Waveforms
Switching Waveforms MRST ADDRESS/ DATA LINES INACTIVE OTHER INPUTS CNTINT CYC2 B0–B3 ADDRESS 1 Latency DATA Notes 22. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge. 23. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH. 24. - Page 18 Switching Waveforms (continued) CYC2 ADDRESS (B1) (B1) DATA OUT(B1) ADDRESS (B2) (B2) DATA OUT(B2) Figure 11. Read-to-Write-to-Read (OE = LOW) CYC2 ADDRESS DATA DATA Notes 26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851AV/CY7C0852AV device from this data sheet.
- Page 19 Switching Waveforms (continued) Figure 12. Read-to-Write-to-Read (OE Controlled) CYC2 ADDRESS DATA DATA Figure 13. Read with Address Counter Advance CYC2 ADDRESS CNTEN DATA x–1 READ EXTERNAL ADDRESS Document #: 38-06070 Rev. *H READ WRITE COUNTER HOLD READ WITH COUNTER CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [25, 28, 30, 31] READ...
- Page 20 Switching Waveforms (continued) Figure 14. Write with Address Counter Advance CYC2 ADDRESS INTERNAL ADDRESS CNTEN DATA WRITE EXTERNAL ADDRESS Figure 15. Disabled-to-Read-to-Read-to-Read-to-Write CYC2 ADDRESS DATA DATA DISABLED Document #: 38-06070 Rev. *H WRITE WITH WRITE COUNTER COUNTER HOLD READ READ CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [31]...
- Page 21 Switching Waveforms (continued) Figure 16. Disabled-to-Write-to-Read-to-Write-to-Read CYC2 ADDRESS DATA DATA DISABLED Figure 17. Disabled-to-Read-to-Disabled-to-Write CYC2 ADDRESS DATA DATA DISABLED Document #: 38-06070 Rev. *H WRITE READ READ DISABLED CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV READ WRITE READ WRITE READ READ Page 21 of 32 [+] Feedback...
- Page 22 Switching Waveforms (continued) Figure 18. Read-to-Readback-to-Read-to-Read (R/W = HIGH) CYC2 CNTEN ADDRESS COUNTER INTERNAL ADDRESS DATA INCREMENT Document #: 38-06070 Rev. *H NO OPERATION READ READ READBACK INCREMENT CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV READ READ INCREMENT INCREMENT Page 22 of 32 [+] Feedback...
- Page 23 Switching Waveforms (continued) CYC2 ADDRESS INTERNAL ADDRESS CNTEN SRST HRST CNTRST DATA [34] DATA COUNTER RESET ADDRESS 0 Notes 32. CE = B0 – B3 = LOW; CE = MRST = CNT/MSK = HIGH. 33. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. 34.
- Page 24 Switching Waveforms (continued) Figure 20. Readback State of Address Counter or Mask Register CYC2 EXTERNAL ADDRESS –A INTERNAL ADDRESS CNTEN DATA LOAD READBACK EXTERNAL COUNTER ADDRESS INTERNAL ADDRESS Notes 35. CE = OE = B0 – B3 = LOW; CE = R/W = CNTRST = MRST = HIGH.
- Page 25 Switching Waveforms (continued) Figure 21. Left_Port (L_Port) Write to Right_Port (R_Port) Read CYC2 L_PORT ADDRESS CKHZ L_PORT DATA CYC2 R_PORT ADDRESS R_PORT DATA Notes 39. CE = OE = ADS = CNTEN = B0 – B3 = LOW; CE 40. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t 41.
- Page 26 Switching Waveforms (continued) Figure 22. Counter Interrupt and Retransmit CYC2 CNT/MSK CNTEN COUNTER INTERNAL 1FFFC 1FFFD ADDRESS CNTINT Notes 42. CE = OE = B0 – B3 = LOW; CE = R/W = CNTRST = MRST = HIGH. 43. CNTINT is always driven. 44.
- Page 27 Switching Waveforms (continued) Figure 23. MailBox Interrupt Timing CYC2 L_PORT 3FFFF ADDRESS CYC2 R_PORT ADDRESS Table 7. Read/Write and Enable Operation (Any Port) Inputs Notes 46. CE = OE = ADS = CNTEN = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. 47.
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Page 28: Ordering Information
Ordering Information 256K × 36 (9M) 3.3V Synchronous CY7C0853AV Dual-Port SRAM Speed Package Ordering Code (MHz) Diagram CY7C0853AV-133BBC 51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch CY7C0853AV-133BBI 51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch CY7C0853AV-133BBXI CY7C0853AV-100BBC 51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch... -
Page 29: Package Diagrams
Package Diagrams Figure 24. 172-Ball FBGA (15 x 15 x 1.25 mm) (51-85114) Document #: 38-06070 Rev. *H CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV 51-85114-*B Page 29 of 32 [+] Feedback... - Page 30 Package Diagrams Figure 25. 176-Pin Thin Quad Flat Pack (24 × 24 × 1.4 mm) (51-85132) Document #: 38-06070 Rev. *H CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV 51-85132-** Page 30 of 32 [+] Feedback...
- Page 31 Document History Page Document Title: CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV, FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM Document Number: 38-06070 Submis- Orig. of REV. ECN NO. sion Date Change 127809 08/04/03 210948 See ECN 216190 See ECN YDT/Dcon Corrected Revision of Document. CMS does not reflect this rev change 231996 See ECN 238938...
- Page 32 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless wireless.cypress.com Memories memory.cypress.com...
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