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Features
■
True dual-ported memory cells which enable simultaneous
access of the same memory location
■
4, 8 or 16K × 16 organization
[1]
■
(CY7C024AV/024BV
/ 025AV/026AV)
■
4 or 8K × 18 organization (CY7C0241AV/0251AV)
■
16K × 18 organization (CY7C036AV)
■
0.35 micron CMOS for optimum speed and power
■
High speed access: 20 and 25 ns
■
Low operating power
❐
Active: I
= 115 mA (typical)
CC
= 10 μA (typical)
❐
Standby: I
SB3
Logic Block Diagram
R/W
L
UB
L
CE
L
LB
L
OE
L
[2]
IO
–IO
8/9L
15/17L
[3]
IO
–IO
0L
7/8L
12/13/14
[4]
A
–A
0L
11/1213L
[4]
A
–A
0L
11/12/13L
CE
L
OE
L
R/W
L
SEM
L
[5]
BUSY
L
INT
L
UB
L
LB
L
Notes
1. CY7C024AV and CY7C024BV are functionally identical.
2. IO
–IO
for x16 devices; IO
–IO
8
15
9
3. IO
–IO
for x16 devices; IO
–IO
0
7
0
8
4. A
–A
for 4K devices; A
–A
for 8K devices; A
0
11
0
12
5. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06052 Rev. *J
8/9
8/9
IO
Control
Address
True Dual-Ported
Decode
12/13/14
for x18 devices.
17
for x18 devices.
–A
for 16K devices.
0
13
•
198 Champion Court
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port
■
Fully asynchronous operation
■
Automatic power down
■
Expandable data bus to 32 bits, 36 bits or more using Master
and Slave chip select when using more than one device
■
On chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Separate upper byte and lower byte control
■
Pin select for Master or Slave (M/S)
■
Commercial and industrial temperature ranges
■
Available in 100-pin Pb-free TQFP and 100-pin TQFP
IO
Control
Address
RAM Array
Decode
12/13/14
Interrupt
Semaphore
Arbitration
M/S
•
San Jose
Static RAM
R/W
R
UB
R
CE
R
LB
R
OE
[2]
8/9
IO
–IO
8/9L
15/17R
[3]
8/9
IO
–IO
0L
7/8R
12/13/14
[4]
A
–A
0R
11/12/13R
[4]
A
–A
0R
11/12/13R
CE
R
OE
R
R/W
R
SEM
R
[5]
BUSY
R
INT
R
UB
R
LB
R
,
CA 95134-1709
•
408-943-2600
Revised December 10, 2008
R
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Related Manuals for Cypress Semiconductor CY7C0241AV
Summary of Contents for Cypress Semiconductor CY7C0241AV
- Page 1 ■ 4, 8 or 16K × 16 organization ■ (CY7C024AV/024BV / 025AV/026AV) ■ 4 or 8K × 18 organization (CY7C0241AV/0251AV) ■ 16K × 18 organization (CY7C036AV) ■ 0.35 micron CMOS for optimum speed and power ■ High speed access: 20 and 25 ns ■...
-
Page 2: Pin Configurations
95 94 93 92 89 88 83 82 81 80 79 78 77 76 CY7C025AV (8K × 16) 31 32 36 37 38 43 44 45 46 47 48 49 50 CY7C0241AV/0251AV/036AV BUSY BUSY Page 2 of 19 [+] Feedback... - Page 3 Figure 2. 100-Pin TQFP (Top View) 95 94 93 92 89 88 83 82 81 80 79 78 77 76 CY7C0241AV (4K × 18) CY7C0251AV (8K × 18) 27 28 31 32 36 37 38 43 44 45 46 47 48 49 50...
-
Page 4: Selection Guide
83 82 81 80 79 78 77 76 CY7C036AV (16K × 18) 27 28 31 32 36 37 38 43 44 45 46 47 48 49 50 CY7C024AV/024BV/025AV/026AV CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV CY7C0241AV/0251AV/036AV BUSY BUSY CY7C0241AV/0251AV/036AV Unit μA Page 4 of 19... -
Page 5: Pin Definitions
BUSY Architecture CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and 16K words of 16 and 18 bits each of dual-port RAM cells, IO and address lines, and control signals (CE, OE, RW). These control pins permit independent access for reads or writes to any location in memory. - Page 6 7. Busy CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within t other, the busy logic determines which port has access. If t violated, one port definitely gains permission to the location, but it is not predictable which port gets that permission.
- Page 7 No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore-free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore-free CY7C0241AV/0251AV/036AV Operation –IO Deselected: Power Down Deselected: Power Down Write to Upper Byte Only Write to Lower Byte Only...
-
Page 8: Maximum Ratings
DC Input Voltage Output Current into Outputs (LOW) ... 20 mA Static Discharge Voltage... > 2001V Latch-up Current... > 200 mA Operating Range Range Commercial [16] Industrial + 0.5V CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV =3.3V) [17] –0.3 –10 –10 Com’l. [16] Ind. Com’l. [16] Ind. -
Page 9: Switching Characteristics
3 ns 3 ns CY7C024AV/024BV/025AV/026AV Description is less than t and t HZCE LZCE HZOE CY7C0241AV/0251AV/036AV 3.3V R1 = 590Ω OUTPUT C = 5 pF R2 = 435Ω (c) Three-State Delay (Load 2) (Used for t , and t HZWE... -
Page 10: Data Retention Mode
SEM Address Access Time Data Retention Mode CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV are designed for battery backup. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention,... -
Page 11: Switching Waveforms
LZCE [29, 31, 32, 33] LZCE LZCE . This waveform cannot be used for semaphore reads. . To access semaphore, CE = V , SEM = V CY7C0241AV/0251AV/036AV [29, 30, 31] [29, 32, 33] HZCE HZOE DATA VALID HZCE HZCE... - Page 12 ) of a LOW CE or SEM and a LOW UB or LB. or (t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can CY7C0241AV/0251AV/036AV [34, 35, 36, 37] [40]...
- Page 13 Document #: 38-06052 Rev. *J CY7C024AV/024BV/025AV/026AV VALID ADRESS DATA VALID SWRD WRITE CYCLE READ CYCLE MATCH MATCH = CE = HIGH. CY7C0241AV/0251AV/036AV [43] DATA VALID [44, 45, 46] Page 13 of 19 [+] Feedback...
- Page 14 DATA IN ADDRESS BUSY DATA OUTL Figure 13. Write Timing with Busy Input (M/S=LOW) BUSY Note 47. CE = CE = LOW. Document #: 38-06052 Rev. *J CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV MATCH VALID MATCH [47] VALID Page 14 of 19 [+] Feedback...
- Page 15 BUSY is asserted. Document #: 38-06052 Rev. *J CY7C024AV/024BV/025AV/026AV ADDRESS MATCH ADDRESS MATCH or t ADDRESS MISMATCH or t ADDRESS MISMATCH CY7C0241AV/0251AV/036AV [48] [48] Page 15 of 19 [+] Feedback...
- Page 16 Document #: 38-06052 Rev. *J CY7C024AV/024BV/025AV/026AV Figure 16. Interrupt Timing Diagram [49] [50] [49] [50] ) is deasserted first. or R/W ) is asserted last. CY7C0241AV/0251AV/036AV READ 7FFF (OR 1/3FFF) READ 7FFE OR 1/3FFE) Page 16 of 19 [+] Feedback...
-
Page 17: Ordering Information
Ordering Code CY7C026AV-20AC CY7C026AV-20AXC CY7C026AV-20AXI CY7C026AV-25AC CY7C026AV-25AXC CY7C026AV-25AI CY7C026AV-25AXI 4K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code CY7C0241AV-20AC CY7C0241AV-25AC 8K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code CY7C0251AV-20AC CY7C0251AV-25AC Document #: 38-06052 Rev. *J CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Package... -
Page 18: Package Diagram
CY7C036AV-20AC CY7C036AV-25AC CY7C036AV-25AXC CY7C036AV-25AI Package Diagram Figure 17. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06052 Rev. *J CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Package Name Package Type 51-85048 100-Pin Thin Quad Flat Pack 51-85048 100-Pin Thin Quad Flat Pack... - Page 19 Document History Page Document Title: CY7C024AV/024BV/025AV/026AV, CY7C0241AV/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Document Number: 38-06052 Orig. of Submission Rev. ECN No. Change 110204 122302 128958 237622 See ECN 241968 See ECN 276451 See ECN 279452 See ECN 373580...
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