Cypress Semiconductor CY62147DV30 Specification Sheet

Features
• Temperature Ranges
— Industrial: –40°C to +85°C
— Automotive-A: –40°C to +85°C
— Automotive-E: –40°C to +125°C
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62147CV25, CY62147CV30, and
CY62147CV33
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = f
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball VFBGA and
non Pb-free 44-pin TSOPII
• Byte power-down feature
Functional Description
The CY62147DV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
Logic Block Diagram
A
10
A
A
A
A
A
A
A
A
A
A
Pow er
Circuit
Note:
1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05340 Rev. *F
max
[1]
DATA IN DRIVERS
9
8
7
6
256K x 16
5
RAM Array
4
3
2
1
0
COLUMN DECODER
CE
-
Down
• 198 Champion Court
4-Mbit (256K x 16) Static RAM
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O
0
pedance state when: deselected (CE HIGH), outputs are dis-
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A ). If Byte High Enable (BHE) is LOW, then data
17
from I/O pins (I/O through I/O
8
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62147DV30 is available in a 48-ball VFBGA, 44 Pin
TSOPII packages.
BHE
BLE
,
• San Jose CA 95134-1709
CY62147DV30
®
) in portable
through I/O ) are placed in a high-im-
15
through I/O
0
) is written into the location
15
through A ).
0 17
to I/O . If Byte High Enable (BHE) is
0 7
to I/O
8
I/O –I/O
0 7
I/O –I/O
8 15
BHE
WE
CE
OE
BLE
• 408-943-2600
Revised August 31, 2006
), is
7
0
. See
15
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