Cypress Semiconductor CY7C1324H Specification Sheet

Features
• 128K x 18 common I/O
• 3.3V core power supply
• 3.3V/2.5V I/O supply
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• "ZZ" Sleep Mode option
Functional Description
The CY7C1324H is a 128K x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
Logic Block Diagram
A0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BW
B
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-00208 Rev. *B
2-Mbit (128K x 18) Flow-Through Sync SRAM
®
[1]
ADDRESS
REGISTER
A[1:0]
Q1
BURST
COUNTER AND
LOGIC
CLR Q0
DQ ,DQP
B B
WRITE REGISTER
DQ ,DQP
A A
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
• 198 Champion Court
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE ), depth-expansion Chip Enables (CE
1
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW , and BWE ), and Global Write ( GW ). Asynchronous
[A:B]
i nputs include the Output Enable (OE) and the ZZ pin . The
CY7C1324H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1324H operates from a +3.3V core power supply
while all outputs may operate with either a +3.3V or +2.5V
supply. All inputs and
JESD8-5-compatible.
DQ ,DQP
B B
WRITE DRIVER
MEMORY
SENSE
ARRAY
AMPS
DQ ,DQP
A A
WRITE DRIVER
,
• San Jose CA 95134-1709
CY7C1324H
and CE ), Burst
2 3
outputs are JEDEC-standard
OUTPUT
DQs
BUFFERS
DQP
A
DQP
B
INPUT
REGISTERS
• 408-943-2600
Revised April 26, 2006
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