Cypress Semiconductor CY7C1310BV18 Specification Sheet

Features
■ Separate independent read and write data ports
❐
Supports concurrent transactions
■ 250 MHz clock for high bandwidth
■
2-word burst on all accesses
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 500 MHz) at 250 MHz
■ Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■
Synchronous internally self-timed writes
■
Available in x8, x9, x18, and x36 configurations
■ Full data coherency, providing most current data
■ Core V = 1.8V (±0.1V); IO V
DD
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■
Variable drive HSTL output buffers
■
JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1310BV18 – 2M x 8
CY7C1910BV18 – 2M x 9
CY7C1312BV18 – 1M x 18
CY7C1314BV18 – 512K x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
Cypress Semiconductor Corporation
Document #: 38-05619 Rev. *F
= 1.4V to V
DDQ DD
250 MHz
250
x8 735
x9 735
x18 800
x36 900
• 198 Champion Court
CY7C1310BV18, CY7C1910BV18
CY7C1312BV18, CY7C1314BV18
18-Mbit QDR™-II SRAM 2-Word

Functional Description

The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and
CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has data outputs to
support read operations and the write port has data inputs to
support write operations. QDR-II architecture has separate data
inputs and data outputs to completely eliminate the need to
"turn-around" the data bus required with common IO devices.
Access to each port is accomplished through a common address
bus. The read address is latched on the rising edge of the K clock
and the write address is latched on the rising edge of the K clock.
Accesses to the QDR-II read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are provided with DDR interfaces. Each
address location is associated
(CY7C1310BV18), 9-bit words (CY7C1910BV18), 18-bit words
(CY7C1312BV18), or 36-bit words (CY7C1314BV18) that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K and C and C), memory bandwidth is maximized
while simplifying system
"turn-arounds".
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
200 MHz 167 MHz
200
630
630
675
750
,
• San Jose CA 95134-1709
Burst Architecture
with two 8-bit
design by eliminating
Unit
167 MHz
550 mA
550
600
650
• 408-943-2600
Revised June 2, 2008
words
bus
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