Analog Devices ADuCM362 Hardware Reference Manual page 153

Hardware Reference Manual
WAKE-UP TIMER
Wake-Up Timer Clear Interrupt Register
Address: 0x40002530, Reset: Not Applicable, Name: T2CLRI
Table 186. T2CLRI Register Bit Descriptions
Bits Name
[15:5] Reserved
4 ROLL
3 WUFD
2 WUFC
1 WUFB
0 WUFA
Ensure that the register write fully completes before returning from the interrupt handler. Use the data synchronization barrier (DSB) instruction
if necessary. See the Interrupts/Wake-Up Signals
Wake-Up Timer Compare Register A
Address: 0x4000253C, Reset: 0x1900, Name: T2WUFA0
Address: 0x40002540, Reset: 0x0000, Name: T2WUFA1
T2WUFAx registers can be written to while the timer is enabled. T2WUFA0 must be written to first and when T2WUFA1 is written to both
registers values are changed. If a small value is required the a write of 0x0000 to T2WUFA1is sufficient for T2WUFA0 to be updated. T2WUFAx
can be written to whether or not the STOPINC (T2CON[11]) bit is set. If set to 1, the STOPINC (T2CON[11]) bit stops T2WUFAx from being
incremented by hardware.
T2WUFAx is an asynchronous register in the 32 kHz clock domain; therefore, read it twice to confirm that the correct value is read.
Table 187. T2WUFA0 Register Bit Descriptions
Bits Name
[15:0] VALUE
Table 188. T2WUFA1 Register Bit Descriptions
Bits Name
[15:0] VALUE
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Description
Unused bit locations.
Interrupt clear bit for when counter rolls over. Only occurs in free running mode.
0: cleared automatically after synchronization.
1: clear a ROLL interrupt flag.
T2WUFD interrupt flag.
0: cleared automatically after synchronization.
1: clear a T2WUFD interrupt flag.
T2WUFC interrupt flag.
0: cleared automatically after synchronization.
1: clear a T2WUFC interrupt flag.
T2WUFB interrupt flag.
0: cleared automatically after synchronization.
1: clear a T2WUFB interrupt flag.
T2WUFA interrupt flag.
0: cleared automatically after synchronization.
1: clear a T2WUFA interrupt flag.
section for a DSB code example.
Description
Lower 16 bits of Compare Register A
Description
Upper 16 bits of Compare Register A
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