Pwm Memory Mapped Registers - Analog Devices ADuCM362 Hardware Reference Manual

Hardware Reference Manual
PWM
When the interrupt generation is enabled (PWMCON0[10]) and the counter value for Pair 2 changes from PWM2LEN to 0, it also generates the
IRQPWM2 interrupt.
The interrupt is cleared by setting PWMCLRI[2].
In H-bridge mode, Pair 0 and Pair 1 are used in the bridge configuration and generate 1 interrupt only, IRQPWM0. While Pair 0 and Pair 1 are
in H-bridge mode, Pair 2 can be used in standard mode and it generates the IRQPWM2 interrupt.

PWM MEMORY MAPPED REGISTERS

Table 199. TPWM Memory Mapped Registers Address Table (Base Address: 0x40001000)
Offset Name
0x000 PWMCON0
0x004 PWMCON1
0x008 PWMCLRI
0x010 PWM0COM0
0x014 PWM0COM1
0x018 PWM0COM2
0x01C PWM0LEN
0x020 PWM1COM0
0x024 PWM1COM1
0x028 PWM1COM2
0x02C PWM1LEN
0x030 PWM2COM0
0x034 PWM2COM1
0x038 PWM2COM2
0x03C PWM2LEN
1
RW8 is eight bits, read or write.
PWM Control Register 0
Address: 0x40001000, Reset: 0x0020, Name: PWMCON0
Table 200. PWMCON0 Register Bit Descriptions
Bit Position Name
15 SYNC
14 Reserved
13 PWM5INV
12 PWM3INV
11 PWM1INV
10 PWMIEN
9 ENA
[8:6] PRE
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Description
PWM Control Register 0
Trip control register
PWM interrupt clear
Compare Register 0 for PWM0 and PWM1
Compare Register 1 for PWM0 and PWM1
Compare Register 2 for PWM0 and PWM1
Period value register for PWM0 and PWM1
Compare Register 0 for PWM2 and PWM3
Compare Register 1 for PWM2 and PWM3
Compare Register 2 for PWM2 and PWM3
Period value register for PWM2 and PWM3
Compare Register 0 for PWM4 and PWM5
Compare Register 1 for PWM4 and PWM5
Compare Register 2 for PWM4 and PWM5
Period value register for PWM4 and PWM5
Description
PWM synchronization.
0: ignore transitions on the PWMSYNC pin.
1: all PWM counters are reset on the next clock edge after the detection of a falling edge on the PWNSYNC pin.
Reserved.
Pair 2 low-side polarity (PWM5). Available in standard mode only.
0: PWM5 is normal.
1: invert PWM5.
Pair 1 low-side polarity (PWM3). Available in standard mode only.
0: PWM3 is normal.
1: invert PWM3.
Pair 0 low-side polarity (PWM1). Available in standard mode only.
0: PWM1 is normal.
1: invert PWM1.
0: disables the PWM interrupts.
1: enables PWM interrupts.
If HOFF = 0 and HMODE = 1. Available in H-bridge mode only.
0: disable PWM outputs.
1: enable PWM outputs.
PWM clock prescaler. Sets UCLK divider.
ADuCM362/ADuCM363
Access Default
RW 0x0012
1
RW8 0x0000
W 0x0000
RW 0x0000
RW 0x0000
RW 0x0000
RW 0x0000
RW 0x0000
RW 0x0000
RW 0x0000
RW 0x0000
RW 0x0000
RW 0x0000
RW 0x0000
RW 0x0000
Rev. B | 162 of 170