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DIDS-402-2MIO
Para 3-17/Para 3-6.3
LOGICAL "0" FOR LWL
,
EOLG
r-----·-·· - ,
I
I
SHIFT-
REG ISTER
NORMAL
I
~I--~
I
I
L -_____
-r----~--~
I
I
I
I
I
I
I
DELAY LINE
I
KEYBOARD
I
EOLG
I
I
I
I
I
L
DISPLAY LOGIC
I
_ _ _ _ _ _ _ _ ---1
010567-13
Figure 3-17.
Display Editing Delete Mode
The operation of the character entry register can be explained easily.
(The character entry and readout registers are both located on circuit board A 13. )
Assume that the desired message is the word
I
CAT
t
and that the
I
C
I
(in the
form of six-bit digital information) is already circulating in the refresh memory
and is on display.
When the
t
C
I
was entered, the cursor automatically stepped
right one character slot.
When the
I
A
I
key on keyboard assembly A 11 is pressed.
the six digital bits, 10000 I, are applied simultaneously to the character entry
register. which consists of one AND gate for each of these six bits followed by
one flip-flop (or register) for each of these six bits (figure 3-10).
When the six
AND gates receive the
I
write 'pulse (this will happen immediately after the
I
C
I
passes through the character entry register because the curSor appears in the
next character slot), the six bits will be inserted into the flip-flops and will be
shifted at the phase 2 clock-pulse rate through the editing logic into refresh
storage (figure 3-18).
3-23
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