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DIDS ... 402 -2M 10
Para 3-7.9
3-7.9Clocked-Tvpe Flip-Flop.
The symbol shown below represents a clocked-
type flip-flop.
The circuit features an AND gate input and two flip-flops con-
nected as a master-slave combination.
The master fUp-flop stores the input
information wp.en the clock voltage is high and transfers it to the slave when the
clock voltage is low.
Direct (unclocked) set and clear pulses are also provided.
The unclockedpulses are used on the jam terminals of the flip-flop and will
override the clocked input.
A low signal on jam input pin 10 will force output
pin 9 low. and a low signal on jam input pin 5 will force output pin 6 low.
3-36
GATE
INPUT
CLOCK
GATE
INPUT
010567-110
3
""\
4
.J
2
II
'\
12
)
JAM
10
6
OUTPUT
945
9
OUTPUT
5
JAM
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