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DIDS;;.402.-2.M10
Para 3-1
An output from the display logic circuit (part of board A13) is fed to the
dataphone inte rface storage registers on board A 12.
Three storage registers
are used to smooth the data so that it can be transmitted at a slower rate over
the telephone line.
Since the line transmits up to 1200 bits/second (this corre-
sponds to 833 JJ.s /bit), the information from the input to the character readout
register (part of board A 13), which is at a rate of 3. 43 IJ.s Ibit,is stored in three
consecutive storage registers.
The message is then picked
off
at the reduced
rate of 12.00 bits / second.
When the mes sage is being received. this process is
reversed.
The dataphone interface mode control and timing section of board
A 12 provides or uses the following functions:
a.
A 12.00-Hz counter which controls the bit transmission rate
into the phone line
b.
The start-of-message control circuit
c.
The end-of-message control circuit
d.
The carriage return decode circuit in the transmit and receive
modes
e.
The parity generator and parity check circuits
Low voltage power supply A4 furnishes a +22vdc, +100 vdc, +5 vdc,
-2.2 vdc, and two
6.
3 vac outputs.
High voltage power supply AS furnishes
+12 kvdc, +500 vdc, and
-1.
2 kvdc outputs.
3-1 DISPLAY TERMINAL CHARACTER GENERATION (Figure 3-1)
When the 'A' key on keyboard assembly A 11 is pressed, the binary signal
for,' A
I
is put on the six data lines as follows:
Lead
Signal Level
FXO
1
FXl
0
FX2
0
FYO
0
FYI
0
FY2.
1
The six-bit digital information is applied to the character entry and readout
register (part of circuit board A 13), which causes the bits to be placed in
sequence.
The data is then fed through a portion of the display logic (also part
of circuit board A
13)
to delay-line refresh-storage A 15.
3-2
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