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DIDS-402-2MIO
Section
3
SECTION 3
THEOR Y OF OPERATION
This chapter contains theory of operation.
The major components and
signal flow are shown in figure 3-1, a simplified block diagram.
Keyboard assembly A 11 provides a specific six-bit digital code for each
character.
The character is inserted into delay-line refresh-storage A 15 where
it circulates continually around the refresh memory loop.
It
is amplified after
the delay-line attenuation and fed out once/frame to digital-to-analog (D/ A con-
verter circuits in monoscope deflection amplifier A3.
The purpose of the monoscope deflection amplifier is to convert the digital
information (which represents the letter
1
A
I ,
for example) figure 3-2 to analog
information and to develop monoscope X - and Y -deflection voltages which will
cause the monoscope beam to paint across the letter 'A
1.
The
1
A
I
output from
the monoscope is then amplified by monoscope preamplifier A 7 and video ampli-
fier AS before it is applied to the cathode of display CRT V2.
The system is synchronized by the master oscillator circuit on circuit
board A 14.
The oscillator on the circuit board drives the timing circuits to
provide the following signals.
a.
Timing pulses that control when the keyboard character is to
be inserted into the register
b.
Horizontal amplifier signals for the horizontal sweep on the dis-
play CRT
c.
Vertical amplifier signals for the vertical sweep on the display
CRT
d.
Blanking pulses
The presentation on the display consists of 13 horizontal sweeps approxi-
mately 0.3 inch apart.
The 583-kHz sine wave is applied to the minor vertical
deflection coil, increasing the apparent line width to a letter height of 0.17 inch.
This sinusoidal signal, (known as the minor vertical expansion voltage) cor-
responds to the sine wave that is sweeping over the letter
I
A
I .
The resulting
video signal is amplified and applied to the display CRT, thus duplicating this
letter on the CRT.
When the XMIT (on keyboard assembly A II) is pressed, the information
is extracted from delay-line memory circuit A 15 and processed by the display
logic circuit on circuit board A 13, the control logic circuit on board A 12, and
discrete circuits on board A14.
The information, in the form
oia
series of
digital signals, is dispatched from the Display Terminal.
The operation is as
follows.
3-1
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