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DIDS-40Z-ZMIO
Fig. 3-181Para 3-6.4
I--
ONE CHARACTER TIME
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CHARACTER"
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CHARACTER "A" ENTERED HERE
CLEAR PULSE
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WRITE PULSE
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REGISTER CLOCK
010567-41
Figure 3 .. 18.
Character Entry Timing
3-6.4
Data
Transmission and Receipt Logic.
The following paragraphs describe ..
the storage registers, the IZO-character-second timing control. the transimit-
receive mode control, and the dataphone drivers and detectors.
The action of
these circuits will be discussed in the following order: when equipment isl in the
transmit mode, when equipment is in the receive mode, word format and t>arity
(or error detection), and modem control signals.
3-Z4
a.
Transmission of message.
The purpose of the regiSters is to:
provide what is called smoothing of the data.
Since access to the
data in the refresh memory loop occurs only once per frame,
enough data must be extracted at the time the cursor is found to
supply the 1200 bits/second (this corresponds to 833 I..I.s/bit) until
the cursor comes around again. one frame period later.
In other
words, when access to the data occurs, enough data must be ex-
tra.cted and stored to feed out at the 1200-Hz transmission rate
until access to the delay line data. is again possible.
Between
I
access times, 18 bits will be sent out at the lower transmission
frequency.
Therefore, at least 18 bits must be stored for smooth
operation (hence the term smoothing).
Three registers are pro-
vided, each of which will store six bits (figure 3 -19).
The steering
logic is simply an electronic switch whkh selects either the mes'"-
sage going from the delay line to the telephone line (XMT -transmit).
or the message coming from the telephone line to the delay line
(RCV -receive).
Three steering logic circuits are controlled b'f the
transmit-receive mode control logic circuit.
Storage registers
No. 2 and No. 3 consist of six flip-flops, and storage register No. I
consists of seven flip-flops which receive and store, the six binary
bits representing a character until the shift-out pulses are applied.
(The additional flip-flop in storage register No. 1 adds a seventh bit
for compatibility with ASCII.)
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