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D1DS-402-2MIO
Para 3-6.4
b.
Reception of message.
When a message is sent from the computer,
the first character is the STX code, the second is the displayad-
dress code, and the third is the first character of the text.
Each
character contains 10 bits: a start bit, seven data bits, a parity
bit, and a stop bit.
The start bit of each character is used to sync
the incoming data to the D1DS-400.
If the start-of-message and
the proper display address codes are not present, storage register
No. 1 does not shift, and therefore all succeeding characters are
ignored.
The incoming data is code converted at register No. 1
by shifting seven bits/character into the register and six bits/
character out.
The 2
5
bit is ignored when register No.
1
is shifting
data into register No.
2 (figu
re 3-20).
Data enters the memory
loop at a maximum rate of two characters/frame.
If registers No. 3
and 2 contain a character, when the cursor begins to enter the read-
out register. both characters will enter the memory loop.
The cur-
sor is stepped right automatically each time a character enters the
memory loop.
When the message is concluded, the ETX code is de-
coded and enters the ETX control circuit.
This causes storage
register No. 1 to stop shifting and no further information is sent
into the refresh memory loop.
The circuits are freed from the
control of the computer and returned to the operator who may
transmit another message if desired.
c.
Word format and parity.
As previously mentioned, a character
code is carried internally as six bits. Since the standard ASCll
coding uses seven bits, a code conversion from six to seven bits
must be performed in storage register No. 1.
The total trans-
mitted character code, which contains 10 bits, begins with a start
bit (a logical 0).
This is followed by the seven-bit character
code, a parity bit, and the stop bit (a logical 1).
Since this is an
even parity system, the parity bit is generated so that the total
count of logical lIs in the transmitted word (excluding start and
stop bits) is an even number.
In the receive mode, parity is
checked in the same way.
If the count of lIs is not an even num-
ber, the error code is substituted for the character code received.
Thus, the operator knows that a malfunction has occurred.
He can
then obtain clarification by repeating the transmit-receive proce-
dure.
.
d.
Modern control signals.
When the XM1T key is depressed, a
Request-to-Send signal level is sent to the modem.
When the sig-
nals Clear-to-Send and Data-Carrier-Detect are received from the
modem (and only when the two are present), the Display Terminal
will transmit data.
The ETXcode, when decoded in register No.1,
removes the Request-to-Send signal; this terminates the transmit
mode.
When the Data-Carrier-Detect signal is received from the
modem and the Request-to-Send signal is not present, the Display
Terminal is in the receive mode.
The Data-Terminal-Ready signal
3-27
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