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3. You must be sure that the calibration is carried out with a fully charged battery, otherwise the charg-
ing voltage will be false by the lower chemical inner resistance of the lead-acid element!
4. Once calibrated, the charging voltage has
to be
monitored for a period of at least 12 hours (always in
the fully charged state).
NOTE: The lead-acid battery is a long-life, maintenance-free accumulator which has a nominal voltage
of 12 Vdc and a current capacity of 2 Ah (2 ampere/hour).
6.
Battety/Mains Operation Mode Detection (schematics 13.8V Batt. charger & power supply)
The batterylmains detection is purely based on 1 diode and 1 data selector/MUX IC on the pPcb. The
Anode of diode D4 is "LOW once the AT-6 works on the battery (no mains). When the mains is ON, the
battery is charged over point "B" by a voltage corresponding to ~ 1 3 . 8 Vdc, the Anode of D4 is now
connected to around 14.8 ..15 Vdc. The path of the MAINS "0N"detection started at point "C" where
~ 1 4 . 8 Vdc is connected to D14 cathode (LL4148), this point is called " B A T OPERATION ON/OFF. The
Anode of D14 is directly connected to the pProcessor Pcb over the backplane main connector ST6 17a, c
to pPcb Europe type connector ST-2 pin 28c. The signal "BAT" provided on the pPcb by D14, is then
connected to pin
#
10 of a quad
2
input data selector/MUX (three state outputs). Pin
#
10 of the HC257
MUX is connected to a 1 0 W pull-up resistor connected to Vdd (+5Vdc), therefore when the mains in ON,
D4 Cathode has about 14.8..15 Vdc thus will not conduct and the Data line input
#
10 (on the schematic
defined as input 38) will be tied up to +5Vdc over the Pull-up resistor. On the other hand
if
the mains is
OFF, the diode will conduct to GND and pin # 10 of the HC257 MUX will change to LOW (4.5Vdc). The
change of status of the MUX input
#
10 is then interpreted as a 4 Bit nibble (D8..D11) transferred to the
data bus therefore indicating the status of the battery mode.
NOTE: With a standard measuring tool like an oscilloscope, you may not clearly identify the nibble
status change on the Data bus when toggling between the modes.
A
logic analyzer would be a
better adapted tool for that kind of digital analysis. This is why it would be preferable to limit the
check to the input of the MUX gate (pin
#lo).
-3-
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