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Glossary
A
Ampere
LCRR
Length Count Recall Register
AAR
Operand 2 Address Register
LIO
Load Input/Output
ac
Alternating Current
Lo
Low
Addr
Address
LP DAR
Line Printer Data Address Register
adj
Adjust
LPIAR
Line Printer Image Address Register
ALO
Automated Logic Diagram
LSR
Local Store Register
ALU
Arithmetic and Logic Unit
MAP
Maintenance Analysis Procedures
APL
Advance Program Level
MES
Miscellaneous Equipment Specification
Arith
Arithmetic
MFCU
Multi-Function Card Unit
ARR
Address Recall Register
MLC
Machine Level Control
ASCII
American Standard Code for Information
Mnem
Mnemonic
Interchange
MPCAR
MFCU Punch Data Address Register
Asynchronous
Without regular time relationships; unexpected
MPTAR
MFCU Print Data Address Register
or unpredictable with respect to the execution
MRDAR
MFCU Read Data Address Register
of a program instruction.
MST
Monolithic System Technology
BAR
Operand 1 Address Register
mV
Millivolt
BCD
Binary Coded Decimal
ns
Nanosecond
Bit
Binary digit; smallest unit of information
oc
Overcurrent
BM
Bill of Material
Op
Operation; Operand
BSCA
Binary Synchronous Communications Adapter
ov
Overvoltage
BSM
Basic Storage Module
p
Parity
Byte
Eight bits of information plus parity bit
PAIR
Product Analysis Incident Reprot
CB
Circuit Breaker
PCB
Printer Control Board
CE
Customer Engineer
PEB
Printer Electronic Board
Channel
A hardware device that connects the CPU and
PG
Parity Generation
main storage with the 1/0 control units
POT
Potentiometer
cm
Centimeter
P/S
Cond
Condition
PSR
Program Status Register
CPU
Processing Unit
PSS
Print Subscan
CRR
Condition Recall Register
PTR
Printer
Ctrl
Control
Rd
Read
DAR
Data Address Register
REA
Request for Engineering Action
DBI
Data Bus In
Reg
Register
DBO
Data Bus Out
RPQ
Request Price Quotation
DFCR
Data File Control Address Register
SAR
Storage Address Register
DFDR
Data File Data Address Register
SIO
Start Input/Output
Disp
Display
SLD
Solid Logic Dense
DRR
Data Recall Register
SLT
Solid Logic Technology
EBCDIC
Extended Binary Coded Decimal Interchange
SMS
Standard Modular System
Code
SS
Single Shot
EC
Engineering Change
Sync
Synchronize
ECA
Engineering Change Announcement
Sys
System
FBM
Field Bill of Material
S/Z
Sense-lnht"bit
FE
Field Engineering
TIO
Test Input/Output and Branch
FEALD
Field Engineering Automated Logic Diagram
TP
Test Point
hex
Hexadecimal
UV
Under voltage
Hi
High
v
Volts
IAR
Instruction Address Register
Vac
Volts Alternating Current
Instr
Instruction
Vdc
Volts Direct Current
Interrupt
An asynchronous occurrence which causes the
wr
write
central processor to cease its normal execution
XR
Index Register
of instructions and barnch out to a new instruc-
XRD
X-Read
tion stream. Interrupts are caused by several
XWR
X-Write
different and unrelated situations.
YRD
Y-Read
1/0
Input/Output
YWR
Y-Write
IPL
Initial Program Load
z
Inhibit
K
Kilo, Thousand
·Equals
LCR
Length Count Register
>
Greater than
<
Less Than
5410 FEMM (1/71) iii
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