IBM 5410 Maintenance Manual page 46

Processing unit
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In the alter SAR position, the address setup in the address/
data switches is transferred into SAR by the start key and
the current !AR-instruction address register {Pl, P2,
or
interrupt level).
If
the start key is held down, alter SAR has
the ability of displa'ying in the A register the data that has
been set in the data switches.
In the alter storage position, pressing the start key transfers
data (previously set up in the rightmost two address/data
switches) into the A register. Releasing the key causes this
data to be placed in the storage location specified by SAR
and in to the
Q
register.
In the display storage position, pressing the start key trans-
fers the contents of the storage location specified by SAR
into the B register. When the key is released, these contents
are rewritten into storage and transferred into the Q register.
2. 1.2.4 LSR Display Selector
This rotary switch selects the local store register (LSR) to
be displayed in position
2
of the display switch. The
LSRs that can be displayed are: instruction address register
(IAR), address recall register (ARR), index register 1 (XRl),
and index register 2 (XR2). The selected LSR is displayed
whenever the CPU is not in CPU or 1/0 cycles. When this
switch is in the normal position, as it should be when the
system is in operation, the CPU controls the selection and
display of LSRs.
Refer to section
2.5
for the procedure to display other
LS Rs.
2. 1.2.
5 System Reset Key
When this pushbutton is pressed, it resets all 1/0 and CPU
registers, controls, and status registers, including the pro-
gram status register (PSR). System reset also resets the
current IAR (Pl or P2 IAR) and the MFCU read address
register to zero. System reset is operable only when the
CE mode selector is set to the process mode.
2.1.2.6
Check Reset Key
This pushbutton resets the processor and 1/0 check con-
ditions. Check reset removes the current error conditions
and allows the processor to reswne its operation after the
start key is pressed. It also resets the system
power~heck
function and allows a 'power on' retry.
2-6
2; 1.2.7 Storage Test Switch
This two position switch allows storage to be altered or
displayed according to the position selected. In the step
position, each time the start key is pressed, a storage
location is accessed. In the run position, when the start key
is pressed, core storage is exercised by accessing either the
same location repetitively or all of core sequentially.
2.1.2.8
Address Increment Switch
This switch allows address incrementing when in the CE
test modes of alter or display storage. With the switch on,
the contents of SAR are incremented by 1 after each storage
access. When the switch is off, SAR is not incremented.
2.1.2.9
Address Compare Switch
This switch allows a compare of the address/data switch
setting and the register display when the register display is
turned to SAR. When the address compare switch is in the
run position, the address switch setting is compared to SAR
through the register display, but no processor stop is initiated
when a match occurs. The matched signal is provided as a
sync point.
When the switch is in the stop position, a match of the ad-
dress switches and the register display causes a processor
stop at the completion of the storage read/write cycle. The
processor is restarted by pressing the start key. 1/0 data
transfers take place without loss of information. The
contents of the SAR do not necessarily match the setting of
the address switches when the processor stops.
2.1.2.101/0
Overlap Switch
This switch modifies control of the system so that 1/0
operations can be executed in either an overlap or a
non-overlap mode. With the switch turned to the normal
position of on, 1/0 operations are executed in an overlap
mode. When the switch is turned off, 1/0 operation is
completed before the next sequential instruction is executed.
2.1.2.111/0
Check Switch
This switch, when set to stop, forces the processor to an
immediate stop on an 1/0 error. The console display is
frozen to indicate the processor status at the time the error
stop occurred. For normal operation, this switch is set to
run.

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