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SENSE INSTRUCTION FORMATS
Op Code
Q
Code
Command
lop
I
a
I
Displacement
I
DA
M N
/
0
7
9
11 12 13 15 16
23
~!o
Direct
Address;ng~
Indexed by XR1
B~
Indexed by XR2
Note: For explanation of Sense Bytes (2), check individual 1/0 sections.
(N code 0 is keyboard sense.)
Figure 1-8. Sense 1/0 (SNS) Instruction Format
5410CPU SENSE
Op
QCode
Operand 1
Code
DA
M
N
0
78
11
12
13 15 16
30
Operand 1
=
2 bytes Direct addressing
l
B_yte 1
=
O_Q_erand 1 address
70
Operand 1
=
1 byte Indexed by XR-1
J
Byte 2
=
OJ!_erand 1 address-1
BO
Operand 1
=
1 byte Indexed by XR-2
0000
Device address CPU (0)
0
Must be zero
Low Core Address
H~h
Core Address
000
Byte 2 (EB2)
Byte 1 (EB 1)
0
l
0
J
1
Address
1
Address
2
switch
2
switch
3
1
3
3
4
l
4
l
*
5
Address
5
Address
6
switch
6
switch
7
2
7
4
xx xx
xxxx
-Operand address Tsense bytes destinations)
*
Note: All other N codes invalid
Figure 1-9. 5410 Sense Bytes
1-12
(1/71)
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