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BSCA SENSE
-··
. .
Op
OCode
Operand
1
Code
DA
M
N
0
7 8
11 12 13
15 16
30
.Operand 1
=
2 bytes Direct addressing
l
Byte 1
=
Operand 1 address
70
Operand 1
=
1 byte Indexed by XR-1
l
Byte 2
=
Operand 1 address-1
BO
Operand 1
=
1 byte Indexed by XR-2
1000
Device address BSCA (8)
0
Must be zero
Low Core Address
High Core Address
Byte 2 (EB2)
Byte 1 (EBl)
000
0 Reserved
0 Reserved
1 Bit time counter 4
1 Reserved
2 Bit time counter 2
2 Reserved
II
3 Bit time counter 1
3 Reserved
4 Reserved
4 Block cycle steal request
(ITB, BCC or VRC check)
5 Transmit trigger
5 LSR/shift reg parity check
6 Receive trigger
6 I /0 cycle steal overrun
7 CE SNS bit
7 DBI parity check
001
Stop address register
010
Transition address
r~ister
011
0 Timeout
0 Reserved
1 CRC/LRC/VRC
1 Reserved
2 Adapter check on trans- 2 Reserved
mit
3 Adapter check on re-
3 Reserved
ceive
I
4 Invalid ASCII
4 Reserved
I
character
5 Abortive disconnect
5 Reserved
6 Disconnect timeout
6 Data set ready
7 Reserved
7 Data line occu_Eied
100
Current address re_g_ister
101
Invalid
110
0
0
~
)
1
I
2
3 (
CRC high
3 (
CRC low
I
(zeros for
4 (
ASCII)
4 (
( L RC for ASCII)
I
~
I
~
I
i
7
7 '
111
Invalid
xx xx
xx xx
Operand address (sense byte destination)
Figure 1-16. BSCA Sense Bytes
5410 FEMM (1/71)
1-19
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