IBM 5410 Maintenance Manual page 20

5424 MFCU SENSE
Op
OCode Operand 1
Code
DA
M N
0
78 11 12 13 15 16
30
Operand 1
=
2 bytes Direct addressing
1
Byte 1
=
Operand 1 address
70
Operand 1
=
1 byte Indexed byXR-1
I
B_yte 2
=
O_gerand 1 address-1
BO
Operand 1
=
1 byte Indexed by XR-2
1111
Device address for MFCU (F)
0
Must be zero
Low Core Address
H~h
Core Address
000 Byte 2 (EB2)
Byte 1 (EB 1)
0 Punch CB
0 Hopper 1 or 2 magnet
1 Punch strobe
1 Hopper cell covered
2 Punch magnet one 2 Gear count 1, 3, 5, 7, 9, 11
3 Ind 1 Byte 2 bit 3 3 Read cell one exposed
(spare)
4 Print time 4 Read cell 18 exposed
5 Print fire CB 5 Allow read
6 Print magnet 1 (A 1) 6 Hopper CB
9(A2)
7 Ind 1 Byte 2 Bit 7
7 Ind 1 Byte 1 Bit 7 (spare)
(spare)
001 0 Corner kick magnet
0 Punch registration roll 1 or 2
1 Print stepper clutch 1 Prepunch cell covered
magnet
2 Post-print cell covered 2 Punch gate magnet
3 Print inject CB 3
Punch eject roll magnet
4 Print kick CB
4 Punch stepper roll magnet
5 Print stepped CB 5 Corner cell covered
6 Print allow, punch 6 Punch stepper CB
execute
7 Ind 2 Byte 2 Bit 7
7 Ind 2 Byte 1 Bit 7 (spare)
(spare)
011
0 Print buffer 1 busy
0 Read check
1
Print buffer 2 busy 1 Punch check
2 Card in wait 1
2 Punch invalid
3
Card in wait 2 3 Print data check
4 Reserved 4 Print clutch check
5 Hopper cycle not 5 Hopper check
complete
6 Card in transport 6 Feed check
counter bit 2
7 Card in transport 7 No-op
counter bit 1
010 Invalid
Stores register
100
MFCU _e_rint address
~ister
101 MF CU read address
~ster
contents at
110
MFCU Qunch address
re_Biste~
operand address 1 and
111
Invalid
operand address 1 minus one.
xx xx xx xx Operand address (sense bytes destination)
Figure 1-11. 5424 MFCU Sense Bytes
1-14 (1/71)