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Machine Cycle
Clock
Load SAR
R/W Select
Data from Stor
Store Pulse
i.------------
1.52 us
0
2
3
4
5
6
7
8
0
I
ADDA
I
MISC
COMPUTE
ADDA LO MOD
I
ADDA HI MOD
I
_}\~~~~~~~~(\
680
ns - - - - - -
_ _ /
R
\1...---_----1/
W
\...___ _ _ _ _
l---480
ns
______________
---1;----,~---_-_-_--_-_---
,- - -
-
,
I
\
I
New Data to Stor
----------------.-1
LSR Select
XADDR
x
x
x
ADDA
x
ADDA
LSR Write
r\
r'"\
I
\
I
\
l
I
~
I\
LO
~------(\'--HI_
A Reg In-Gate
_ /
x
x
FORCE 1
\
B Reg In-Gate
,,'~s;---x ~D~-
__
X
LSR LO
x
LSR HI
\~_
(\
Load A
&
B Regs _ _ _ _ _ __,(\..._ _ _ _ _ _,(\
( \ _ _ _ _ _ _,
Binary Subtract
\ ----I
Comp A Reg
-,,---- -,,----,r---
------~t~--------'(
}~--------------------
ALU Output
x
x
x
x
Figure 1-22. CPU Basic Timing
1-24 (1/71)
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