IBM 5410 Maintenance Manual page 31

Processing unit
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LOCAL STORE REGISTERS
BASE SYSTEM
HIGH
LOW
LSR
Acronym
Program level 1 instruction address register
P1-IAR
Program level 1 address recall register
P1-ARR
Operand 2 address register
AAA
Spare
1----
Program level 1 index register 1
P1-XR 1
Length count recall register
Condition recall register
P1-PSR
Operand 1 address register
BAR
MFCU print data address register
MPTAR
Program level 1 index register 2
P1-XR2
II
Line printer data address register
LPDAR
Line printer image address register
LPIAR
MFCU punch data address register
MPCAR
MFCU read address register
MR DAR
Length count registers
Data recal I register
LCR
ORR
Interrupt level 1 instruction address register
IAR-1
Interrupt level 1 address recall register
ARR-1
FEATURE 1
HIGH
I
LOW
LSR
Acronym
Program level 2, instruction address register
P2-IAR
Program level 2, address recall register
Bi-sync comm adapter address register
P2-ARR
~AR
Serial
1/0
channel address register
SIAR
Program level 2 status register
P2-PSR
Interrupt level 4, instruction address register
IAR-4
Interrupt level 4, address recall register
ARR-4
Disk file control address register
DFCR
Program level 2 index register 2
P2-XR2
Spare
Spare
Interrupt level 2, instruction address register
IAR-2
Interrupt level 2, address recall register
ARR-2
Disk file data address register
DFDR
Program level 2, index register 1
P2-XR 1
Interrupt level 0, instruction address register
IAR-0
Interrupt level 0, address recall register
ARR-0
Figure 1-23. Local Storage Registers
5410 FEMM
(1/71)
1-25

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