Advantech IDK-1107WR-50WVB1 User Manual page 19

Note (1) Because this module is operated by DE only mode, Hsync and Vsync
input signals are ignored.
Note (2) The Tv (Tvd+Tvb) must be an integer; otherwise, this module will oper-
ate abnormally.
Note (3) The input clock cycle-to-cycle jitter is defined in the following figures.
Trcl = I T1 – TI
INPUT SIGNAL TIMING DIAGRAM
13 IDK-1107WR-50WVB1 User Manual