Analog Devices Lite ADSP-21371 EZ-KIT System Manual page 40

System Architecture
2-4
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The DAI pins are connected to the AD1835A audio codec, a 26-pin
header, two RCA connectors, audio oscillator output, an external phase
lock loop (PLL) circuit, two LEDs, and two push buttons.
illustrates the EZ-KIT Lite's connections to the DAI interface.
PB_4
DAI20 (SFS45)
PB_3
DAI19 (SCLK45)
DAI18 (SD5B)
SPDIF IN
DAI17 (SD5A)
AUDIO OSC
LED7
DAI16 (SD4B)
DAI15 (SD4A) LED6
DAI14 (SFS23)
DAI13 (SCLK23)
DAI12 (SD3B)
DAI11 (SD3A)
DAI10 (SD2B)
DAI9 (SD2A)
DAI8 (SFS1)
DAI7 (SCLK1)
DAI5 (SD1A)
DAI6 (SD1B)
ELVIS_TRIG
DAI4 (SFS0)
PLLMCLK IN
DAI3 (SCLK0)
PLLMCLK OUT
DAI2 (SD0B)
SPDIF OUT
DAI1 (SD0A)
DSP
Figure 2-2. DAI Connections Block Diagram
To use the DAI for a different purpose, disable any signal driving a DAI
pin with a switch (see "Codec Setup Switch (SW3)" on page
In addition, enables flexible routing of the 12.288 MHz audio oscilla-
SW3
tor's output signal. By default, the
( ) for the AD1835A codec.
MCLK
All of the DAI signals are available externally via the expansion interface
connectors ( ) and 0.1" spaced header (
J1—3
tors can be found in "ADSP-21371 EZ-KIT Lite Schematic" on page
ADSP-21371 EZ-KIT Lite Evaluation System Manual
DAC_LRCLK DAC1
DAC_BCLK DAC2
DAC_SDATA1 DAC3
DAC_SDATA2 DAC4
DAC_SDATA3
DAC_SDATA4
AD1835
ADC_LRCLK ADC
ADC_BCLK
ADC_SDATA1
MCLK
12.288MHz
signal is used as the master clock
SW3
). The pinout of the connec-
P4
Figure 2-2
4x2
RCA
Phono
Jack
OUT
Head-
phone
Jack
1X2
RCA
Phono
Jack IN
2-10).
B-1.