Psoc™ 6 Mcu Power Modes - Infineon AIROC CYW43012 Manual

Low-power system design with AIROC™ Wi-Fi & Bluetooth® combo
chip and PSoC™ 6 MCU
Low-power overview
2.2 PSoC™ 6 MCU power modes
PSoC™ 6 MCU features seven power modes split into system modes that affect the whole device and standard
Arm® CPU modes that affect only one CPU. The system power modes are Low-Power (LP), Ultra-Low-Power
(ULP), Deep Sleep, and Hibernate. The Arm® CPU power modes are Active, Sleep, and Deep Sleep, and are
available in system LP and ULP power modes. See
power reduction techniques.
for representing power mode transitions in a PSoC™ 6 MCU and AIROC™ Wi-Fi & Bluetooth® combo chip design
(Figure 1).
Table 2 Power modes in PSoC™ 6 MCU
Power mode Description
System LP
All resources are available with maximum power and speed.
•
All CPU power modes supported.
•
System ULP
All blocks are available, but core voltage is lowered resulting in
•
reduced high-frequency clock frequencies.
All CPU power modes supported.
•
CPU Active
Normal CPU code execution
•
Available in system LP and ULP power modes
•
CPU Sleep
CPU halts code execution.
•
Available in system LP and ULP power modes
•
CPU Deep
CPU halts code execution.
•
Sleep
Requests system Deep Sleep entry
•
Available in system LP and ULP power modes
•
System Deep
Occurs when all CPUs are in CPU-Deep Sleep
•
Sleep
CPUs, most peripherals, and high-frequency clocks are OFF.
•
Low-frequency clock is ON.
•
Low-power analog and some digital peripherals are available for
•
operation and as wakeup sources.
SRAM is retained.
•
System
CPUs and clocks are OFF.
•
Hibernate
GPIO output states are frozen.
•
Low-power comparator, RTC alarm, and dedicated WAKEUP pins
•
are available to wake up the system.
Backup domain is available.
•
Application note
AN219528
Table 2 summarizes PSoC™ 6 MCU power modes and provides a simplified version
for details on PSoC™ 6 MCU low-power modes and
6
Simplified power
mode
Active mode
Sleep mode
Deep Sleep
Hibernate
002-27910 Rev. *C
2023-05-29