Infineon C166S V1 SubSystem User Manual

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Us er's Ma nual, V 1 .6 , A ugust 2001

C 1 6 6 S V 1 S u b S y s t e m

C 1 6 6 S V 1 S u b S R 1

M i c r o c o n t r o l l e r s

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Table of Contents

Summary of Contents for Infineon C166S V1 SubSystem

Page 1 Us er’s Ma nual, V 1 .6 , A ugust 2001 C 1 6 6 S V 1 S u b S y s t e m C 1 6 6 S V 1 S u b S R 1 M i c r o c o n t r o l l e r s N e v e r s t o p...
Page 2 Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life.
Page 3 Us er’s Ma nual, V 1 .6 , A ugust 2001 C 1 6 6 S V 1 S u b S y s t e m C 1 6 6 S V 1 S u b S R 1 M i c r o c o n t r o l l e r s N e v e r s t o p...
Page 4 Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: ce.cmd@infineon.com...
Page 5: Table Of Contents
User’s Manual C166S V1 SubSystem Table of Contents Page Introduction ..........1-1 The Members of the 16-bit Microcontroller Family .
Page 6 User’s Manual C166S V1 SubSystem Table of Contents Page 3.4.5.2 Hardware Traps ........3-26 3.4.6...
Page 7 User’s Manual C166S V1 SubSystem Table of Contents Page Memory Organization ........4-1 Data Organization in Memory .
Page 8 User’s Manual C166S V1 SubSystem Table of Contents Page EBC Idle State ......... . . 8-30 External Bus Arbitration .
Page 9 User’s Manual C166S V1 SubSystem Table of Contents Page 12.3.2 Auxiliary Timer T5 ........12-34 12.3.3...
Page 10: User's Manual
User’s Manual C166S V1 SubSystem User’s Manual V 1.6, 2001-08...
Page 11: Introduction
• provide system security and fail-safe mechanisms • provide effective means to control (and reduce) the device’s power consumption. About this Manual This manual describes the functionality of the 16-bit microcontroller-subsystem C166S_R1 of the Infineon C166 Family, the C166S-class. User’s Manual V 1.6, 2001-08...
Page 12: The Members Of The 16-Bit Microcontroller Family
Introduction The Members of the 16-bit Microcontroller Family The microcontroller-subsystem of the Infineon 16-bit family has been designed to meet the high performance requirements of real-time embedded control applications. The architecture of this family has been optimized for high instruction throughput and minimum response time to external stimuli (interrupts).
Page 13: Summary Of Basic Features
C166S V1 SubSystem Introduction Summary of Basic Features The C166S is an improved representative of the Infineon family of full featured 16-bit single-chip CMOS (Complementary Metal Oxide Silicon) microcontrollers. It combines high CPU performance with high peripheral functionality. Several key features contribute to the high performance of the C166S bases subsystem (the indicated timings refer to a CPU clock of MHz).
Page 14: Watchdog Timer
User’s Manual C166S V1 SubSystem Introduction Intelligent On-chip Peripherals • General Purpose Timer Unit Timer Block 1: – f maximum resolution PDBUS+/4 – 3 independent timers/counters – Timer/counters can be concatenated – 4 operation modes (timer, gated timer, counter, incremental) –...
Page 15 C166S V1 SubSystem Introduction Complete Development Support For the development tool support of its microcontrollers, Infineon follows a clear third party concept. Currently around 120 tool suppliers world-wide, ranging from local niche manufacturers to multinational companies with broad product portfolios, offer powerful...
Page 16 User’s Manual C166S V1 SubSystem Introduction User’s Manual V 1.6, 2001-08...
Page 17: System Overview
User’s Manual C166S V1 SubSystem System Overview System Overview The architecture of the C166S combines the advantages of both RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) processors in a very well-balanced way. The sum of the features which are combined results in a high performance microcontroller, which is the right choice not only for today’s...
Page 18: Basic Cpu Concepts And Mega Core
User’s Manual C166S V1 SubSystem System Overview Basic CPU Concepts and Mega Core The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated Special Function Registers (SFRs). Additional hardware is provided for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Page 19 User’s Manual C166S V1 SubSystem System Overview If this technique were not used, each instruction would require four machine cycles. This increased performance allows a greater number of tasks and interrupts to be processed. Instruction Decoder Instruction decoding is primarily generated from PLA (Programmable Logic Array) outputs based on the selected opcode.
Page 20 User’s Manual C166S V1 SubSystem System Overview 2.1.3 Extended Bit Processing and Peripheral Control A large number of instructions has been dedicated to bit processing. These instructions provide efficient control and testing of peripherals while enhancing data manipulation. Unlike other microcontrollers, these instructions provide direct access to two operands in the bit-addressable space without requiring to move them into temporary flags.
Page 21 User’s Manual C166S V1 SubSystem System Overview 2.1.4 Consistent and Optimized Instruction Formats To obtain optimum performance in a pipelined design, an instruction set has been designed which incorporates concepts from Reduced Instruction Set Computing (RISC). These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds.
Page 22: Programmable Multiple Priority Interrupt And Pec System
User’s Manual C166S V1 SubSystem System Overview 2.1.5 Programmable Multiple Priority Interrupt and PEC System The following enhancements have been included to allow processing of a large number of interrupt sources: 1. Peripheral Event Controller (PEC): This processor is used to off-load many interrupt requests from the CPU.
Page 23: The C166S System Resources
User’s Manual C166S V1 SubSystem System Overview The C166S System Resources The C166S based subsystem provides a number of powerful system resources designed around the CPU. The combination of CPU and these resources results in the high performance of the members of this controller family.
Page 24: External Bus Interface
User’s Manual C166S V1 SubSystem System Overview 2.2.2 External Bus Interface In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller via its external bus interface.
Page 25: Asynchronous / Synchronous Serial Channel (Asc0)
User’s Manual C166S V1 SubSystem System Overview Peripheral Interfaces The on-chip peripherals generally have two different types of interfaces, an interface to the CPU and an interface to external hardware. Communication between CPU and peripherals is performed through Special Function Registers (SFRs) and interrupts.
Page 26: High Speed Synchronous Serial Channel (Ssc0)
User’s Manual C166S V1 SubSystem System Overview In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers.
Page 27: Parallel Ports (Pports)
User’s Manual C166S V1 SubSystem System Overview Block 2 contains 2 timers/counters with a maximum resolution of f /2. An PDBUS+ additional CAPREL register supports capture and reload operation with extended functionality. The following enumeration summarizes all features to be supported: •...
Page 28: Periodic Wakeup From Idle Or Sleep Mode
User’s Manual C166S V1 SubSystem System Overview 2.2.5 Periodic Wakeup from Idle or Sleep Mode Periodic wakeup from Idle mode or from Sleep mode combines the drastically reduced power consumption in Idle/Sleep mode (in conjunction with the additional power management features) with a high level of system availability. External signals and events can be scanned (at a lower rate) by periodically activating the CPU and selected peripherals which then return to powersave mode after a short time.
Page 29 User’s Manual C166S V1 SubSystem System Overview Power Saving Control (PSC) The idle mode, and the power down mode mode are supported by the power saving control block. Periodic wakeup from Idle mode combines the drastically reduced power consumption in Idle mode (in conjunction with the additional power management features) with a high level of system availability.
Page 30: Clock Generation Unit (Cgu)
User’s Manual C166S V1 SubSystem System Overview The Watchdog Timer is a 16-bit timer, which counts the PDBUS+ clock divided either by 2, 4, 128 or 256. The high byte of the Watchdog Timer register can be set to a predefined reload value (stored in WDTREL) in order to allow further variation of the monitored time interval.
Page 31: Central Processing Unit
User’s Manual C166S V1 SubSystem Central Processing Unit Central Processing Unit The C166S Central Processing Unit (CPU) represents the synthesizable generation of the well-known C166 core family. It has many powerful enhancements while remaining compatible with the C166 family. The new architecture offers a high-performance CPU;...
Page 32 User’s Manual C166S V1 SubSystem Central Processing Unit – 4-stage execution pipeline 7. Address and Data Unit (ADU) – 16-bit arithmetic unit for address generation 8. Arithmetic and Logic Unit (ALU) – 8-bit and 16-bit arithmetic unit – 16-bit barrel shifter –...
Page 33: Register Description Format
User’s Manual C166S V1 SubSystem Central Processing Unit Register Description Format The C166S contains a set of Special-Function Registers (SFRs) and Extended Special- Function Registers (ESFRs) that are described in the respective chapter of this manual. The example below shows how to interpret the format and notation that are used to describe SFRs and ESFRs.
Page 34 User’s Manual C166S V1 SubSystem Central Processing Unit : unchanged [undefined (X) after power up] : defined by reset configuration : bit number of bit [m:n] : bit number of first bit of the bitfield : bit number of last bit of the bitfield...
Page 35: Cpu Special-Function Registers
User’s Manual C166S V1 SubSystem Central Processing Unit CPU Special-Function Registers The core CPU requires a set of CPU Special-Function Registers (CSFRs) to maintain the system state information, to control system and bus configuration, and to manage code memory segmentation and data memory paging. The CPU also uses CSFRs to access the General-Purpose Registers (GPRs) and the System Stack, to supply the ALU with register-addressable constants, and to support multiply and divide ALU operations.
Page 36 User’s Manual C166S V1 SubSystem Central Processing Unit Byte write operations to word wide SFRs via indirect or direct 16-bit (mem) addressing or byte transfers via the PEC force zeros in the non-addressed byte. Byte write operations via short 8-bit (reg) addressing can only access the low byte of an SFR and force zeros in the high byte.
Page 37: Instruction Fetch And Program Flow Control
User’s Manual C166S V1 SubSystem Central Processing Unit Instruction Fetch and Program Flow Control The C166S can fetch on average one 32-bit or two 16-bit instructions via the 32-bit wide Local Memory Bus (LM-Bus) every machine cycle (which equals two clock cycles T1 and T2) to provide a continuous instruction flow.
Page 38 User’s Manual C166S V1 SubSystem Central Processing Unit instruction, or rel = -2 (FE ) for a double-word-sized branch instruction. [Rw]: In this case, the 16-bit branch target instruction address is determined indi- rectly by the contents of a word GPR. In contrast to indirect data addresses, indirectly-specified code addresses are NOT calculated via additional pointer registers (eg.
Page 39: Sequential And Non-Sequential Instruction Flow
User’s Manual C166S V1 SubSystem Central Processing Unit 3.3.2 Sequential and Non-Sequential Instruction Flow Since passing through one pipeline stage takes at least one machine cycle (which equals two clock cycles T1 and T2), any isolated instruction takes at least four machine cycles to be completed.
Page 40 User’s Manual C166S V1 SubSystem Central Processing Unit Table 3-3 shows the standard unconditional branch (branch taken) instruction pipeline, assuming a fast local memory (0/1 waitstates).. Unconditional branches Table 3-3 (LM-Bus, 0/1 waitstate) Clock Cycle LM-Address LM-Data 32bit FETCH n+1==...
Page 41 User’s Manual C166S V1 SubSystem Central Processing Unit Cache Jump Instruction Processing The C166S incorporates a jump cache to optimize conditional jumps, which are processed repeatedly within a loop. Whenever a jump on cache is taken, the extra time to fetch the branch target instruction can be saved and thus the corresponding cache jump instruction in most cases takes only one (unconditional branch) or two (conditional branch) machine cycles.
Page 42 User’s Manual C166S V1 SubSystem Central Processing Unit Table 3-6 shows a standard conditional branch (branch taken and target cached) instruction pipeline, assuming a fast local memory (0/1 waitstates). Table 3-6 Conditional cached branches (LM-Bus, 0/1 waitstate) Clock Cycle Address...
Page 43: Atomic And Extended Instructions
User’s Manual C166S V1 SubSystem Central Processing Unit 3.3.3 ATOMIC and EXTended Instructions ATOMIC and EXTended instructions (ATOMIC, EXTR, EXTP, EXTS, EXTPR, EXTSR) disable the standard and PEC interrupts and class A traps until the completion of the next sequence of instructions. The number of instructions in the sequence may vary from 1 to 4.
Page 44: Code Addressing Via Code Segment And Instruction Pointer
User’s Manual C166S V1 SubSystem Central Processing Unit 3.3.4 Code Addressing via Code Segment and Instruction Pointer The C166S provides a total addressable memory space of 16 MBytes. This address space is arranged as 256 segments of 64 KBytes each. A dedicated 24-bit code address pointer is used to access the memories for instruction fetches.
Page 45 User’s Manual C166S V1 SubSystem Central Processing Unit The Instruction Pointer IP This register determines the 16-bit intra-segment address of the currently fetched instruction within the code segment selected by the CSP register. The IP register is not mapped into the C166S’s address space, and thus it is not directly accessible by the programmer.
Page 46 User’s Manual C166S V1 SubSystem Central Processing Unit The actual code memory address is generated by direct extension of the 16-bit contents of the IP register by the lower byte of the CSP register, as shown in Figure 3-2. There are two modes: Segmented and non-segmented. The mode is selected with the SGTDIS bit in the SYSCON register.
Page 47: The Cpu/System Configuration Register Syscon
User’s Manual C166S V1 SubSystem Central Processing Unit 3.3.5 The CPU/System Configuration Register SYSCON This register is used to configure the C166S. It is bit-addressable and provides general system configuration and control functions. The reset value of register SYSCON depends on the state of the configuration inputs during reset.
Page 48: Interrupt And Exception Execution
User’s Manual C166S V1 SubSystem Central Processing Unit Interrupt and Exception Execution An Interrupt and Exception Handler is responsible for managing all system and core exceptions. There are four different kinds of exceptions that are executed in a similar way: •...
Page 49: Interrupt System Structure
User’s Manual C166S V1 SubSystem Central Processing Unit 3.4.1 Interrupt System Structure The C166S provides up to 112 separate interrupt nodes that may be assigned to 128 arbitration priority levels with 16 interrupt priority groups and 4/8 priorities inside each group.
Page 50 User’s Manual C166S V1 SubSystem Central Processing Unit cycle. However, if an arbitration cycle is currently in progress, the new interrupt request will be delayed till the next arbitration cycle. If an interrupt request (or PEC request) is accepted by the core, the respective interrupt request flag is cleared automatically.
Page 51 User’s Manual C166S V1 SubSystem Central Processing Unit PSW. The CPU denies all requests in case of a cleared IEN flag. If the requester has a lower or equal priority level than current CPU task, the request stays pending. Note: Priority level 0000 is the default level of the CPU.
Page 52: Interrupt Vector Table
User’s Manual C166S V1 SubSystem Central Processing Unit Field Bits Type Description ILVL [5:2] Interrupt Priority Level Highest priority level Lowest priority level GLVL [1:0] Group Priority Level Defines the internal order for simultaneous requests of the same priority. Bit xxIR supports bit-protection The arbitration scheme allows nesting of up to 15 ISRs of different priority levels (level 0 cannot be used;...
Page 53 User’s Manual C166S V1 SubSystem Central Processing Unit Processor Status Word SFR(FF10 Reset value: 0000 ILVL USR0 Field Bits Type Description ILVL [15:12] rwh CPU Priority Level Lowest Priority Highest Priority [11] Interrupt/PEC Enable Flag (globally) Interrupt/PEC requests are disabled...
Page 54: Saving The Status During Interrupt Service
User’s Manual C166S V1 SubSystem Central Processing Unit 3.4.4.1 Saving the Status during Interrupt Service Before an operating system or ITC can actually service a task switch request or interrupt, the CPU must save the current task status. The C166S saves the CPU status (PSW) along with the return address in the system stack.
Page 55 User’s Manual C166S V1 SubSystem Central Processing Unit The C166S makes it possible to switch the complete register bank of CPU registers (GPRs) with a single instruction, so the service routine executes within its own separate context. The instruction “SCXT CP, #New_Bank” pushes the contents of the Context Pointer (CP) into the system stack and loads the CP with the immediate value “New_Bank”.
Page 56: Traps
User’s Manual C166S V1 SubSystem Central Processing Unit 3.4.5 Traps 3.4.5.1 Software Traps The TRAP instruction is used to cause a software call to an ISR. The trap number that is specified in the operand field of the trap instruction determines which vector location of the vector table will be used.
Page 57 User’s Manual C166S V1 SubSystem Central Processing Unit – Undefined opcode – Protection fault – Illegal word operand access – Illegal instruction access – Illegal external bus access The Class B traps share the same interrupt node and interrupt vector. The bit- addressable Trap Flag Register (TFR) allows a trap service routine to identify the trap that caused the exception.
Page 58 User’s Manual C166S V1 SubSystem Central Processing Unit Field Bits Type Description ILLOPA ILLegal word OPerand Access No illegal word operand access event detected Ilegal word operand access event detected ILLINA ILLegal INstruction Access No illegal instruction access detected A branch to an odd address has been attempt.
Page 59 User’s Manual C166S V1 SubSystem Central Processing Unit Exception Condition Trap Trap Trap Trap Flag Vector Number Priority Class A Hardware Traps: Non-Maskable Interrupt NMITRAP II.3 STacK OverFlow STKOF STOTRAP II.2 STacK UnderFlow STKUF STUTRAP II.1 SOFTware BReaK SOFTBRK SBRKTRAP II.0...
Page 60 User’s Manual C166S V1 SubSystem Central Processing Unit STacK OverFlow Trap (STKOF) Whenever the stack pointer SP is decremented to a value less than the value in the stack overflow register STKOV, the STKOF flag in register TFR is set and the CPU will enter the stack overflow trap routine.
Page 61 User’s Manual C166S V1 SubSystem Central Processing Unit During the execution of a Class A trap service routine, any Class B trap will not be serviced until the Class A trap service routine is exited with a RETI instruction. In this case, the Class B trap condition is stored in the TFR but the IP value of the instruction that caused this trap will be lost.
Page 62: Peripheral Event Controller
User’s Manual C166S V1 SubSystem Central Processing Unit 3.4.6 Peripheral Event Controller The Peripheral Event Controller (PEC) “decides” which CPU action is required to manage an interrupt request. It may be either normal interrupt service, or fast data transfer between two memory locations. The C166S PEC controls up to sixteen fast data transfer channels.
Page 63: The Pec Source And Destination Pointers
User’s Manual C166S V1 SubSystem Central Processing Unit 3.4.6.1 The PEC Source and Destination Pointers The PEC channels’ source and destination pointers specify the locations between which the data is to be moved. All pointers are 24 bits wide. The 24-bit source address is stored in the internal DPRAM location SRCPx (lower 16 bits of address) and in the low byte of register PECSNx (highest 8 address bits).
Page 64 User’s Manual C166S V1 SubSystem Central Processing Unit Note: If a word data transfer is selected for a specific PEC channel (i.e. BWT = 0), the respective source and destination pointers must both contain a valid word address that points to an even byte boundary. Otherwise, the Illegal Word Access trap will be invoked when this channel is used.
Page 65 User’s Manual C166S V1 SubSystem Central Processing Unit PECSNx PEC Segment Pointer SFR( Reset value: 0000 DSTSNx SRCSNx Field Bits Type Description DSTSNx [15:8] Destination Pointer Segment Address of Channel Destination Address bits 23-16 SRCSNx [7:0] Source Pointer Segment Address of Channel x Source Address bits 23-16 User’s Manual...
Page 66: Pec Control Registers
User’s Manual C166S V1 SubSystem Central Processing Unit 3.4.6.2 PEC Control Registers Each PEC channel is controlled by the respective PEC channel Control register (PECCx) and a set of source and destination pointers (SRCPx, DSTPx and PECSNx), where “x” stands for the PEC channel number. The PECCx registers control the arbitration priority level assigned to the PEC channels and specifies the action to be performed.
Page 67 User’s Manual C166S V1 SubSystem Central Processing Unit Field Bits Type Description Byte / Word Transfer Selection Transfer a word Transfer a byte COUNT [7:0] PEC Transfer Count Counts PEC transfers and influences the channel´s action The long transfer mode is an optional mode. If the product does not support the long transfer mode for this specific PEC channel, the PT-bit is hardwired to zero.
Page 68: Short Transfer Mode
User’s Manual C166S V1 SubSystem Central Processing Unit 3.4.6.3 Short Transfer Mode If the short transfer mode is enabled by the PT flag (PT = 0) in the PEC control register PECCx, the PEC Transfer Count Field (COUNT) of the PECCx controls directly the action of the respective PEC channel.
Page 69: Long Transfer Mode
User’s Manual C166S V1 SubSystem Central Processing Unit 3.4.6.4 Long Transfer Mode If the long transfer mode is enabled by the PT flag (PT = 1) in the PEC control register PECCx, the PEC Transfer Count Field (COUNT2) of the PECXCx register directly controls the action of the respective PEC channel.
Page 70 User’s Manual C166S V1 SubSystem Central Processing Unit cleared if EOPINT is set to 1. If EOPINT is 0, the request flag will not be cleared and another interrupt request will be generated on the same priority level. The respective PEC channel remains idle and the associated interrupt service routine is activated instead of PEC transfer, because COUNT2 contains the 0000 value.
Page 71: Channel Link Mode For Data Chaining
User’s Manual C166S V1 SubSystem Central Processing Unit 3.4.6.5 Channel Link Mode for Data Chaining Channel linking, if enabled, links two channels together to serve the data transfer requests of one peripheral. The whole data transfer (for example a message) is divided into separately-controlled block transfers.
Page 72 User’s Manual C166S V1 SubSystem Central Processing Unit The channel link feature is supported for all PEC channels, including the new PEC channels 8-15. The following table shows the channels that can be linked together and the channel numbers required to start transfers via linked channels.
Page 73: Pec Channels Assignment And Arbitration
User’s Manual C166S V1 SubSystem Central Processing Unit 3.4.6.6 PEC Channels Assignment and Arbitration The PEC channels can be assigned to arbitration priority levels. All requests with interrupt priority levels 8 to 15 can be associated with the PEC functionality (up to a total of sixteen PEC channels).
Page 74: Programmable End Of Pec Interrupt Level
User’s Manual C166S V1 SubSystem Central Processing Unit 3.4.6.7 Programmable End of PEC Interrupt Level The programmable EOP interrupt supports PEC transfers, which need a high priority level for the transfer request, and which do not need the same priority level for the termination interrupt.
Page 75 User’s Manual C166S V1 SubSystem Central Processing Unit PECISNC PEC Interrupt Sub Node Control SFR( Reset value: 0000 C7IR C7IE C6IR C6IE C5IR C5IE C4IR C4IE C3IR C3IE C2IR C2IE C1IR C1IE C0IR C0IE PECXISNC PEC Interrupt Sub Node Control...
Page 76: Using General-Purpose Registers
User’s Manual C166S V1 SubSystem Central Processing Unit Using General-Purpose Registers The C166S uses several banks of 16 dedicated General Purpose Registers (GPRs) R0, R1, R2... R15 that can be accessed in one CPU cycle. The GPRs are the working registers of the Arithmetic and Logic Units (ALU) and may also serve as address pointers in indirect addressing modes.
Page 77 User’s Manual C166S V1 SubSystem Central Processing Unit Note: If GPRs are used as indirect address pointers, they are always accessed word- wise. For some instructions, only the first 4 GPRs (R0, R1, R2 and R3) can be used as indirect address pointers.
Page 78 User’s Manual C166S V1 SubSystem Central Processing Unit Table 3-10 Addressing modes to Access Word-GPRs Name Physical 8-Bit 4-Bit Description Reset Address Address Address Value (CP)+0 General-Purpose word Register R0 UUUU (CP)+2 General-Purpose word Register R1 UUUU (CP)+4 General-Purpose word Register R2...
Page 79 User’s Manual C166S V1 SubSystem Central Processing Unit Each half of the byte-wise accessible registers has a special name (see table below). Table 3-11 Addressing modes to access Byte-GPRs Name Physical 8-Bit 4-Bit Description Reset Address Address Address Value (CP)+0...
Page 80: Context Switch
User’s Manual C166S V1 SubSystem Central Processing Unit 3.5.1 Context Switch An Interrupt Service Routine (ISR) or a task scheduler of an operating system usually saves the contents of all used registers into the stack, and restores them before returning. The more registers a routine uses, the more time is wasted by saving and restoring.
Page 81 User’s Manual C166S V1 SubSystem Central Processing Unit The C166S switches the complete memory-mapped GPR bank with a single instruction. After switching, the service routine executes within its own separate context. The instruction SCXT CP, #New_Bank pushes the value of the current context pointer (CP) into the system stack and loads CP with the immediate value New_Bank, which selects a new register bank.
Page 82: Data Addressing
User’s Manual C166S V1 SubSystem Central Processing Unit Data Addressing The C166S provides a lot of powerful addressing modes for word-wise, byte-wise and bitwise data accesses (short, long, indirect). The different addressing modes use different formats and have different scopes.
Page 83 User’s Manual C166S V1 SubSystem Central Processing Unit reg: Specifies direct access to any (E)SFR or GPR in the currently active context. The reg value requires 8 bits in the instruction format. Short reg addresses in always specify (E)SFRs. In that case, the factor ∆...
Page 84: Long And Indirect Addressing Modes
User’s Manual C166S V1 SubSystem Central Processing Unit 3.6.2 Long and Indirect Addressing Modes These addressing modes use one of the 4 DPP registers to specify a 24-bit address. Any word or byte data within the entire address space can be accessed with these modes.
Page 85: Addressing Via Data
User’s Manual C166S V1 SubSystem Central Processing Unit 3.6.2.1 Addressing via Data Page Pointer The 4 non-bit-addressable DPP registers select up to 4 different data pages. The lower 10 bits of each DPP register select one of the 1024 possible 16-KByte data pages, while the upper 6 bits are reserved for the future use.
Page 86 User’s Manual C166S V1 SubSystem Central Processing Unit DPP0 Data Page Pointer 0 SFR(FE00 Reset value: 0000 DPP0PN DPP1 Data Page Pointer 1 SFR(FE02 Reset value: 0001 DPP1PN DPP2 Data Page Pointer 2 SFR(FE04 Reset value: 0002 DPP2PN DPP3 Data Page Pointer 3...
Page 87: Dpp Override Mechanism In The C166S
User’s Manual C166S V1 SubSystem Central Processing Unit 3.6.2.2 DPP Override Mechanism in the C166S The C166S provides an override mechanism to temporarily bypass the DPP addressing scheme. The EXTP(R) and EXTS(R) instructions override this addressing mechanism. Instruction EXTP(R) replaces the contents of the DPP register, while instruction EXTS(R) concatenates the complete 16-bit long address with the specified segment base address.
Page 88: Long Addressing Mode
User’s Manual C166S V1 SubSystem Central Processing Unit 3.6.2.3 Long Addressing Mode The long addressing mode uses a 16-bit constant value encoded in the instruction format which specifies the data page offset and the DPP. The long addressing mode is referred to by the mnemonic mem.
Page 89: Indirect Addressing Modes
User’s Manual C166S V1 SubSystem Central Processing Unit 3.6.2.4 Indirect Addressing Modes These addressing modes can be considered as a combination of short and long addressing modes. This means that a long 16-bit address is provided indirectly by the contents of a word GPR that is specified directly by a short 4-bit address (Rw = 0 to 15).
Page 90 User’s Manual C166S V1 SubSystem Central Processing Unit (GPR Pointer) = (GPR Pointer) ± ∆; [optional step!] The following indirect addressing modes are provided: Table 3-14 Indirect addressing modes Mnemonic Particularities [Rw] Most instructions accept any GPR (R15...R0) as indirect address pointer.
Page 91: The System Stack
User’s Manual C166S V1 SubSystem Central Processing Unit 3.6.3 The System Stack A system stack is provided to store return vectors, segment pointers, and processor status for procedures and interrupt routines. The internal system stack can also be used to store data temporarily, or pass it between subroutines or tasks.
Page 92: Stack Overflow And Underflow
User’s Manual C166S V1 SubSystem Central Processing Unit Field Bits Type Description 1111 [15:12] r Fixed at 1111 [11:1] Modifiable portion of register SP Specifies the top of the system stack. Fixed at 0 3.6.3.1 Stack Overflow and Underflow Detection of stack overflow/underflow is supported by two registers, STKOV (STacK OVerflow pointer) and STKUN (STacK UNderflow pointer).
Page 93 User’s Manual C166S V1 SubSystem Central Processing Unit Field Bits Type Description 1111 [15:12] r Fixed at 1111 STKOV [11:1] Modifiable portion of register STKOV Specifies the segment offset address of the lower limit of the system stack. Fixed at ’0’...
Page 94: Linear Stack
User’s Manual C166S V1 SubSystem Central Processing Unit Field Bits Type Description 1111 [15:12] r Fixed at 1111 STKUN [11:1] Modifiable portion of register STKUN Specifies the segment offset address of the upper limit of the system stack. Fixed at 0 STKUN can be updated via any instruction capable of modifying an SFR.
Page 95: Circular (Virtual) Stack
User’s Manual C166S V1 SubSystem Central Processing Unit Note: Stack accesses below the DPRAM area (ESFR space and reserved area) and within address range 00’FE00 and 00’FFFE (SFR space) will have unpredictable results. 3.6.3.3 Circular (Virtual) Stack This basic technique allows pushing until the overflow boundary of the internal stack is reached.
Page 96 User’s Manual C166S V1 SubSystem Central Processing Unit The virtual stack addresses are transformed to physical stack addresses by concatenating the significant bits of SP (see table Table 3-15) with the complementary most significant bits of the upper limit of the physical stack area (00’FBFE ).
Page 97 User’s Manual C166S V1 SubSystem Central Processing Unit internal stack, this circular stack mechanism only requires moving that portion of stack data that is to be re-used (i.e. the upper part of the defined stack area) instead of the whole stack area. Stack data that remain in the lower part of the internal stack need not be moved by the distance of the space being flushed or filled, as the stack pointer automatically wraps around to the beginning of the freed part of the stack area.
Page 98: Data Processing
User’s Manual C166S V1 SubSystem Central Processing Unit Data Processing All standard arithmetic, shift, and logical operations are performed in the 16-bit Arithmetic and Logic Unit (ALU). In addition to the standard ALU, the ALU of the C166S includes bit manipulation, and a multiply-and-divide unit. Most internal execution blocks have been optimized to perform operations on either 8-bit or 16-bit numbers.
Page 99 User’s Manual C166S V1 SubSystem Central Processing Unit Table 3-17 ANSI C data types ANSI C data types Size (bytes) Range CPU data format 0 to 65535U WORD esfr 0 to 65535U WORD signed short -32768 to +32767 WORD unsigned short...
Page 100: Constants
User’s Manual C166S V1 SubSystem Central Processing Unit 3.7.2 Constants In addition to the powerful addressing modes the C166S instruction set also supports word-wide or byte-wide immediate constants. For an optimum utilization of the available code storage, these constants are represented in the instruction formats by either 3, 4, 8 or 16 bits.
Page 101 User’s Manual C166S V1 SubSystem Central Processing Unit All instructions that manipulate single bits or bit groups internally use a read-modify-write sequence that accesses the whole word, which contains the specified bit(s). This method has several consequences: • Bits can only be modified within the internal address areas, i.e. DPRAM and SFRs.
Page 102: Multiply And Divide Unit
User’s Manual C166S V1 SubSystem Central Processing Unit 3.7.5 Multiply and Divide Unit The C166S has a separated multiply-and-divide unit. The multiplication is executed within five machine cycles, while a division takes 20 machine cycles. The multiply-and- divide process is interruptible by an interrupt that has a higher priority level than the current CPU level.
Page 103 User’s Manual C166S V1 SubSystem Central Processing Unit the 32-bit dividend before the division has started. After any division, MDL represents the 16-bit quotient. Multiply/Divide Low Word SFR(FE0E Reset value: 0000 Field Bits Type Description [15:0] Low part of MD The low order 16 bits of the 32-bit multiply and divide register MD.
Page 104 User’s Manual C166S V1 SubSystem Central Processing Unit Field Bits Type Description MDRIU Multiply/Divide Register In Use Cleared when register MDL is read via software. Set when register MDL or MDH is written via software, or when a multiply or divide instruction is executed.
Page 105 User’s Manual C166S V1 SubSystem Central Processing Unit JMPR cc_NV, COPYL ;Test for only 16-bit result R3, MDH ;Move high portion of MD COPYL: R4, MDL ;Move low portion of MD, Clears MDRIU RESTORE: SAVED, DONE ;Test if MD registers were saved ;Restore registers...
Page 106: The Processor Status Word Register (Psw)
User’s Manual C166S V1 SubSystem Central Processing Unit 3.7.6 The Processor Status Word Register (PSW) The bit-addressable Processor Status Word register reflects the current status of the microcontroller. Two groups of bits represent the current ALU status and the current CPU interrupt status.
Page 107 User’s Manual C166S V1 SubSystem Central Processing Unit Field Bits Type Description Carry Flag No carry/borrow bit produced Carry/borrow bit produced Negative Result ALU result is not negative ALU result is negative ALU Status (N, C, V, Z, E, MULIP) The condition flags (N, C, V, Z, E) within the PSW indicate the ALU status resulting from the ALU operation last performed.
Page 108 User’s Manual C166S V1 SubSystem Central Processing Unit For Boolean bit operations with only one operand, the C-flag is always cleared. For Boolean bit operations with two operands, the C-flag represents the logical ANDing of the two specified bits. • V-Flag: The addition, subtraction, and 2's complement operations set the V-flag to 1 if the result exceeds the range of 16-bit signed numbers for word operations (–8000...
Page 109 User’s Manual C166S V1 SubSystem Central Processing Unit be reasonably used for table search operations. In all other cases, the E-flag value depends on the value of the source operand to signify whether or not the end of a search table is reached. If the value of the source operand of an instruction equals the...
Page 110: Instruction Pipeline
User’s Manual C166S V1 SubSystem Central Processing Unit Instruction Pipeline The instruction pipeline of the C166S partitions instruction processing into four stages. Each of these has a separate task: 1st –>FETCH: In this stage, the instruction selected by the Instruction Pointer (IP) and the Code Segment Pointer (CSP) is fetched from either the internal local memory, DPRAM, or external memory.
Page 111: General Considerations
User’s Manual C166S V1 SubSystem Central Processing Unit 3.8.1.1 General considerations Due to pipeline, Read operation, performed by next instruction, can takes place before a Write operation, performed by the earlier instruction. While this fact can lead to some general problems, an extra CPU hardware - the forwarding mechanism - deals with the operand read/write addresses, and also controls the pipeline when needed.
Page 112 User’s Manual C166S V1 SubSystem Central Processing Unit • Address Pointer Updating Indirect addressing modes use a GPR value to generate the address of the source and/ or destination operand. If this GPR is updated explicitly by the preceding instruction, one NOP instruction is automatically inserted.
Page 113 User’s Manual C166S V1 SubSystem Central Processing Unit • Explicit Stack Pointer Updating Neither the RET nor POP instruction is capable of correctly using a new SP register value, which is to be updated by an immediately preceding instruction. Thus, in order to...
Page 114 User’s Manual C166S V1 SubSystem Central Processing Unit • Controlling Interrupts Software modifications (implicit or explicit) of the PSW are done in the execute phase of instructions. In order to maintain fast interrupt responses, however, the current interrupt prioritization round does not consider these changes, i.e., an interrupt request may be acknowledged after the instruction that disables interrupts via IEN or ILVL, or after the following instructions.
Page 115 User’s Manual C166S V1 SubSystem Central Processing Unit • Initialization of Port Pins Modifications of the direction of port pins (input or output) become effective only after the instruction following the modifying instruction. As bit instructions (BSET, BCLR) use internal read-modify-write sequences accessing the whole port, instructions modifying the port direction should be followed by an instruction that does not access the same port (see example below).
Page 116: Common Portable Solution
User’s Manual C166S V1 SubSystem Central Processing Unit 3.8.1.3 Common portable solution When writing to an external memory location, the time needed before the new value becomes effective depends also on the overall system performance. In general more extra cycle(s) will be needed in case of lower peripheral bus speed to cover the delay additionally caused.
Page 117: Instruction State Times
User’s Manual C166S V1 SubSystem Central Processing Unit 3.8.2 Instruction State Times Instruction pipelining usually reduces the average instruction processing time (typically within a range of 1-4 machine cycles). However, there are some rare cases, where a particular pipeline situation causes the processing time for a single instruction to be extended either by a half or by one machine cycle.
Page 118 User’s Manual C166S V1 SubSystem Central Processing Unit The operand and instruction accesses listed below can extend the execution time of an instruction: • Internal Local Memory operand accesses (same for byte and word operand accesses) • DPRAM operand reads via indirect addressing modes •...
Page 119: Dedicated Csfrs
User’s Manual C166S V1 SubSystem Central Processing Unit Dedicated CSFRs The Constant Zeros Register ZEROS All bits of this bit-addressable register are fixed at 0 by hardware. This register is read- only. Register ZEROS can be used as a register-addressable constant of all zeros for bit manipulation or mask generation.
Page 120 User’s Manual C166S V1 SubSystem Central Processing Unit CPU Identification register CPUID This 16-bit register contains the module and revision number of the implemented C166S module. CPUID CPU Identification Register ESFR(F00C ,E-06 Reset value: 04?? CPUREVNO CPUMODNO Field Bits Type Description...
Page 121: Summary Of Cpu Registers
User’s Manual C166S V1 SubSystem Central Processing Unit 3.10 Summary of CPU Registers This section summarizes all registers in the C166S. There are two kind of registers, the General Purpose Registers (GPR) and the CPU-Special Function Registers (CSFR). The GPRs are the working registers of the arithmetic and logic operations and may be also used as address pointers indirect addressing modes.
Page 122 User’s Manual C166S V1 SubSystem Central Processing Unit The following byte-wise accessible registers have special names. . Table 3-22 Addressing modes to access Byte-GPRs Name Physical 8-Bit 4-Bit Description Reset Address Address Address Value (CP)+0 General-Purpose byte Register RL0 (CP)+1...
Page 123: Core Special Function Registers Ordered By Name
User’s Manual C166S V1 SubSystem Central Processing Unit 3.10.2 Core Special Function Registers Ordered by Name The following table lists all CSFRs in alphabetical order. Bit-addressable CSFRs are marked with the letter “b” in column “Name”. CSFRs within the Extended CSFR-Space (ECSFRs) are marked with the letter “E” in column “8-Bit Address”.
Page 124: Core Special Function Registers Ordered By Address
User’s Manual C166S V1 SubSystem Central Processing Unit 3.10.3 Core Special Function Registers ordered by Address The following table lists all CSFRs which are implemented in the C166S ordered by their physical address. Bit-addressable CSFRs are marked with the letter “b” in column “Name”.
Page 125: Register Overview C166S Interrupt And Peripheral Event Controller
User’s Manual C166S V1 SubSystem Central Processing Unit 3.10.4 Register Overview C166S Interrupt and Peripheral Event Controller The following table lists all xSFRs which are implemented in the C166S Interrupt and Peripheral Event Controller. Table 3-23 Register Overview - C166S Interrupt and Peripheral Event Controller...
Page 126 User’s Manual C166S V1 SubSystem Central Processing Unit User’s Manual 3-96 V 1.6, 2001-08...
Page 127: Memory Organization
User’s Manual C166S V1 SubSystem Memory Organization Memory Organization The memory space of the C166S has a “Von Neumann” architecture. This means that code and data are accessed within the same linear address space. All of the physically separated memory areas, including internal ROM/FLASH/DRAM (where integrated),...
Page 128 User’s Manual C166S V1 SubSystem Memory Organization The C166S has a total addressable memory space of 16 MBytes. This address space is arranged as 256 segments of 64 KBytes each, and each segment is again subdivided into four data pages of 16 KBytes each (see Figure 4-1).
Page 129: Data Organization In Memory
User’s Manual C166S V1 SubSystem Memory Organization Data Organization in Memory Bytes are stored at even or odd byte addresses. Words are stored in ascending memory locations with the low byte at an even byte address, followed by the high byte at the next odd byte address.
Page 130: Internal Local Memory Area
User’s Manual C166S V1 SubSystem Memory Organization Internal Local Memory Area The C166S reserves an address area of variable size (depending on the device configuration) for on-chip Local Memory (LM). The internal LM can be ROM, SRAM, flash or DRAM.
Page 131: Dpram And Sfr-Area
User’s Manual C166S V1 SubSystem Memory Organization DPRAM and SFR-Area The C166S differentiates between the internal data memory (DPRAM) and the internal peripheral areas. The DPRAM and the SFR areas are located within data page 3, and provide fast accesses using one dedicated Data Page Pointer (DPP) (see Figure 4-3).
Page 132 User’s Manual C166S V1 SubSystem Memory Organization 00’FFFF 00’FFFF RAM / SFR Area 00’F000 Area Data Page 3 00’FE00 00’E000 DPRAM 00’FD00 External 00’C000 Data Page 2 00’8000 DPRAM Data Page 1 Internal 00’4000 Program Memory 00’F200 Data Page 0...
Page 133: Pec Source And Destination Pointers
User’s Manual C166S V1 SubSystem Memory Organization When accessing registers in the ESFR area using 8-bit addresses or direct bit addressing, the EXTend Register (EXTR) instruction is required before accessing registers in the ESFR area, in order to switch the short-addressing mechanism from the standard SFR area to the ESFR area.
Page 134: External Memory Space
User’s Manual C166S V1 SubSystem Memory Organization External Memory Space The C166S CPU can use an address space of up to 16 MBytes. Only parts of this address space are occupied by the internal LM, DPRAM and the IO/SFR area. All addresses not used for this kind of on-chip memory or for registers may reference external memory locations.
Page 135: Crossing Memory Boundaries
User’s Manual C166S V1 SubSystem Memory Organization Crossing Memory Boundaries The address space of the C166S CPU is divided implicitly into equally-sized blocks of different granularity and into logical memory areas. Crossing the boundaries between these blocks (code or data) or areas requires special attention to ensure that the controller executes the desired operations.
Page 136: System Stack
User’s Manual C166S V1 SubSystem Memory Organization System Stack The system stack must be defined within the DPRAM. The size of the system stack is controlled by bitfield STKSZ in register SYSCON (see table below). Table 4-1 System stack size <STKSZ>...
Page 137 User’s Manual C166S V1 SubSystem Memory Organization the current DPP register contents). Additionally, each bit in the currently active register bank can be accessed individually. The C166S supports register bank (context) switching. Multiple memory-mapped register banks can physically exist within the DPRAM at the same time. Only the register bank selected by the CP register is active at a given time, however.
Page 138: Sfr / Esfr Table
User’s Manual C166S V1 SubSystem Memory Organization SFR / ESFR Table The following table lists all SFRs/ESFRs which are implemented in the C166S V1 SubS R1 ordered by their physical address. Table 4-2 SFR/ESFR Table (ordered by physical address) Physical...
Page 139 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value F030 ESFR F032 ESFR F034 ESFR F036 ESFR F038 ESFR F03A ESFR F03C ESFR F03E...
Page 140 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value F068 COMDATA ESFR Cerberus Communication Mode 0000 Register F06A RWDATA ESFR Cerberus RW Mode Data...
Page 141 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value F09E ESFR F0A0 ESFR F0A2 ESFR F0A4 ESFR F0A6 ESFR F0A8 ESFR F0AA ESFR F0AC...
Page 142 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value F0CC IRQ106IC ESFR IRQ106 Interrupt Control 0000 Register F0CE IRQ107IC ESFR IRQ107 Interrupt Control 0000...
Page 143 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value F0F4 DSWEVT ESFR Specifies action if DEBUG 0000 instruction is executed F0F6 reserved ESFR reserved - do not use...
Page 144 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value F128 IRQ68IC ESFR-b 94 IRQ68 Interrupt Control Register 0000 F12A IRQ69IC ESFR-b 95 IRQ69 Interrupt Control Register 0000...
Page 145 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value F162 IRQ49IC ESFR-b B1 IRQ49 Interrupt Control Register 0000 F164 IRQ50IC ESFR-b B2 IRQ50 Interrupt Control Register 0000...
Page 146 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value F19A WDTIC ESFR-b CD Watchdog Timer Interrupt Control 0000 Register F19C S0TBIC ESFR-b CE ASC0 Transmit Buffer Interrupt...
Page 147 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value F1CE ESFR-b E7 F1D0 ESFR-b E8 F1D2 ESFR-b E9 F1D4 ESFR-b EA F1D6 ESFR-b EB...
Page 148 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value FE04 DPP2 CPU Data Page Pointer 2 0002 Register (10 bits) FE06 DPP3 CPU Data Page Pointer 3...
Page 149 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value FE32 FE34 FE36 FE38 FE3A FE3C FE3E FE40 GPT Timer 2 Register 0000 FE42 GPT Timer 3 Register...
Page 150 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value FE6A FE6C FE6E FE70 FE72 FE74 FE76 FE78 FE7A FE7C FE7E FE80 FE82 FE84 FE86...
Page 151 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value FEA4 FEA6 FEA8 FEAA FEAC FEAE Watchdog Timer Register (RO) 0000 FEB0 S0TBUF Serial Channel 0 Transmit Buffer...
Page 152 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value FED8 PECSN4 PEC Segment No. Register 0000 FEDA PECSN5 PEC Segment No. Register 0000 FEDC PECSN6 PEC Segment No.
Page 153 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value FF0E SFR-b CPU Multiply Divide Control 0000 Register FF10 SFR-b CPU Program Status Word 0000...
Page 154 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value FF44 T4CON SFR-b GPT Timer 4 Control Register 0000 FF46 T5CON SFR-b GPT Timer 5 Control Register...
Page 155 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value FF70 S0EIC SFR-b ASC0 Error Interrupt Control 0000 Register FF72 SSC0TIC SFR-b SSC0 Transmit Interrupt Control...
Page 156 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value FFA4 SFR-b FFA6 SFR-b FFA8 PECISNC SFR-b PEC Interrupt Subnode Control 0000 Register FFAA SFR-b...
Page 157 User’s Manual C166S V1 SubSystem Memory Organization Table 4-2 SFR/ESFR Table (ordered by physical address) (cont’d) Physical Name Type 8-bit Description Reset Address Addr Value FFDA reserved SFR-b reserved - do not use FFDC reserved SFR-b reserved - do not use...
Page 158 User’s Manual C166S V1 SubSystem Memory Organization The following table lists all SFRs/ESFRs which are implemented in the C166S V1 SubS R1 ordered by their name. Table 4-3 SFR/ESFR Table (ordered by name) Name Physical Type 8-bit Description Reset Address...
Page 159 User’s Manual C166S V1 SubSystem Memory Organization Table 4-3 SFR/ESFR Table (ordered by name) (cont’d) Name Physical Type 8-bit Description Reset Address Addr Value F0F8 ESFR Instruction pointer register 0000 DIPX F0FA ESFR Instruction pointer register 3000 extension DP0H F102...
Page 160 User’s Manual C166S V1 SubSystem Memory Organization Table 4-3 SFR/ESFR Table (ordered by name) (cont’d) Name Physical Type 8-bit Description Reset Address Addr Value IRQ17IC FF7A SFR-b IRQ17 Interrupt Control Register 0000 IRQ18IC FF7C SFR-b IRQ18 Interrupt Control Register 0000...
Page 161 User’s Manual C166S V1 SubSystem Memory Organization Table 4-3 SFR/ESFR Table (ordered by name) (cont’d) Name Physical Type 8-bit Description Reset Address Addr Value IRQ46IC F198 ESFR-b CC IRQ46 Interrupt Control Register 0000 IRQ47IC F188 ESFR-b C4 IRQ47 Interrupt Control Register 0000...
Page 162 User’s Manual C166S V1 SubSystem Memory Organization Table 4-3 SFR/ESFR Table (ordered by name) (cont’d) Name Physical Type 8-bit Description Reset Address Addr Value IRQ75IC F136 ESFR-b 9B IRQ75 Interrupt Control Register 0000 IRQ76IC F138 ESFR-b 9C IRQ76 Interrupt Control Register 0000...
Page 163 User’s Manual C166S V1 SubSystem Memory Organization Table 4-3 SFR/ESFR Table (ordered by name) (cont’d) Name Physical Type 8-bit Description Reset Address Addr Value IRQ102IC F0C4 ESFR IRQ102 Interrupt Control 0000 Register IRQ103IC F0C6 ESFR IRQ103 Interrupt Control 0000 Register...
Page 164 User’s Manual C166S V1 SubSystem Memory Organization Table 4-3 SFR/ESFR Table (ordered by name) (cont’d) Name Physical Type 8-bit Description Reset Address Addr Value FFCC SFR-b Port 6 Register (8 bits) PECC0 FEC0 PEC Channel 0 Control Register 0000 PECC1...
Page 165 User’s Manual C166S V1 SubSystem Memory Organization Table 4-3 SFR/ESFR Table (ordered by name) (cont’d) Name Physical Type 8-bit Description Reset Address Addr Value PECSN5 FEDA PEC Segment No. Register 0000 PECSN6 FEDC PEC Segment No. Register 0000 PECSN7 FEDE PEC Segment No.
Page 166 User’s Manual C166S V1 SubSystem Memory Organization Table 4-3 SFR/ESFR Table (ordered by name) (cont’d) Name Physical Type 8-bit Description Reset Address Addr Value S0TBIC F19C ESFR-b CE ASC0 Transmit Buffer Interrupt 0000 Control Register S0TBUF FEB0 Serial Channel 0 Transmit Buffer...
Page 167 User’s Manual C166S V1 SubSystem Memory Organization Table 4-3 SFR/ESFR Table (ordered by name) (cont’d) Name Physical Type 8-bit Description Reset Address Addr Value FE42 GPT Timer 3 Register 0000 T3CON FF42 SFR-b GPT Timer 3 Control Register 0000 T3IC...
Page 168 User’s Manual C166S V1 SubSystem Memory Organization Table 4-3 SFR/ESFR Table (ordered by name) (cont’d) Name Physical Type 8-bit Description Reset Address Addr Value XBCON3 F118 ESFR-b 8C XBUS Control register 3 0000 XBCON4 F11A ESFR-b 8D XBUS Control register 4...
Page 169: Interrupt Vector Table
User’s Manual C166S V1 SubSystem Memory Organization Interrupt Vector Table The interrupt vector table is an instruction table. For each interrupt a 4 byte range is reserved for instructions. Up to 112 interrupt nodes and 16 trap entries are defined for a C166S V1 SubS R1 based product.
Page 170 User’s Manual C166S V1 SubSystem Memory Organization Table 4-4 Interrupt Vector Table (cont’d) (sorted by trap number) Signal Name Source of Interrupt Interrupt Control Vector Trap (Interrupt IF) Register Location 0038 003C irq_i[16] Product Interrupt Request 16 IRQ16IC 0040 irq_i[17]...
Page 171 User’s Manual C166S V1 SubSystem Memory Organization Table 4-4 Interrupt Vector Table (cont’d) (sorted by trap number) Signal Name Source of Interrupt Interrupt Control Vector Trap (Interrupt IF) Register Location per_irq_i[12] ASC0 Receive S0RIC 00AC per_irq_i[13] ASC0 Error S0EIC 00B0...
Page 172 User’s Manual C166S V1 SubSystem Memory Organization Table 4-4 Interrupt Vector Table (cont’d) (sorted by trap number) Signal Name Source of Interrupt Interrupt Control Vector Trap (Interrupt IF) Register Location irq_i[42] Product Interrupt Request 42 IRQ42IC 0120 irq_i[43] Product Interrupt Request 43...
Page 173 User’s Manual C166S V1 SubSystem Memory Organization Table 4-4 Interrupt Vector Table (cont’d) (sorted by trap number) Signal Name Source of Interrupt Interrupt Control Vector Trap (Interrupt IF) Register Location irq_i[85] Product Interrupt Request 85 IRQ85IC 0194 irq_i[86] Product Interrupt Request 86...
Page 174 User’s Manual C166S V1 SubSystem Memory Organization The following table lists all possible 97 interrupt source entries, which are available on product level (listed by the interrupt interface signal name). Note: Depending on the number of interrupt configuration not all entries are available...
Page 175 User’s Manual C166S V1 SubSystem Memory Organization Table 4-5 Interrupt Vector Table (cont’d) (sorted by signal name) Signal Name Source of Interrupt Interrupt Control Vector Trap (Interrupt IF) Register Location irq_i[40] Product Interrupt Request 40 IRQ40IC 00F4 irq_i[41] Product Interrupt Request 41...
Page 176 User’s Manual C166S V1 SubSystem Memory Organization Table 4-5 Interrupt Vector Table (cont’d) (sorted by signal name) Signal Name Source of Interrupt Interrupt Control Vector Trap (Interrupt IF) Register Location irq_i[69] Product Interrupt Request 69 IRQ69IC 0154 irq_i[70] Product Interrupt Request 70...
Page 177 User’s Manual C166S V1 SubSystem Memory Organization Table 4-5 Interrupt Vector Table (cont’d) (sorted by signal name) Signal Name Source of Interrupt Interrupt Control Vector Trap (Interrupt IF) Register Location irq_i[98] Product Interrupt Request 98 IRQ98IC 01C8 irq_i[99] Product Interrupt Request 99...
Page 178 User’s Manual C166S V1 SubSystem Memory Organization User’s Manual 4-52 V 1.6, 2001-08...
Page 179: Instruction Set
User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Short Instruction Summary The following compressed cross-reference tables quickly identify a specific instruction and provide basic information about it. Two ordering schemes are included: The first table (two pages) is a compressed cross-reference table that quickly identifies a specific hexadecimal opcode with the respective mnemonic.
Page 180 User’s Manual C166S V1 SubSystem Instruction Set Note: Both ordering schemes (hexadecimal opcode and mnemonic) are provided in more detailed lists in the following sections of this manual. x0 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS MOV x1 NEG NEGB CPLB...
Page 181: Instruction Set Summary
User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary This chapter summarizes the instructions by listing them according to their functional class. This allows to identify the right instruction(s) for a specific required function. The following notes apply to this summary: Data Addressing Modes –...
Page 182 User’s Manual C166S V1 SubSystem Instruction Set #trap7: – Immediate 7-bit trap or interrupt number. Extension Operations The EXT* instructions override the standard DPP addressing scheme: #pag10: – Immediate 10-bit page address. #seg8: – Immediate 8-bit segment address. Branch Condition Codes...
Page 183 User’s Manual C166S V1 SubSystem Instruction Set Mnemonic Addressing ModesBytes Mnemonic Addressing ModesBytes ADD[B] CPL[B] ADDC[B] [Rwi] NEG[B] AND[B] [Rwi+] OR[B] #data3 DIVL SUB[B] DIVLU SUBC[B] #data16 DIVU XOR[B] MULU ASHR CMPD1/2 #data4 ROL / ROR #data4 CMPI1/2 #data16 SHL / SHR BAND bitaddrZ.z...
Page 184 User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary Mnemonic Description Bytes Arithmetic Operations Rw, Rw Add direct word GPR to direct GPR Rw, [Rw] Add indirect word memory to direct GPR Rw, [Rw +] Add indirect word memory to direct GPR and post-...
Page 185 User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Arithmetic Operations (cont’d) ADDCB mem, reg Add direct byte register to direct memory with Carry Rw, Rw Subtract direct word GPR from direct GPR Rw, [Rw]...
Page 186 User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Arithmetic Operations (cont’d) SUBCB reg, mem Subtract direct byte memory from direct register with Carry SUBCB mem, reg Subtract direct byte register from direct memory with Carry...
Page 187 User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Logical Instructions (cont’d) Rw, Rw Bitwise OR direct word GPR with direct GPR Rw, [Rw] Bitwise OR indirect word memory with direct GPR Rw, [Rw +]...
Page 188 User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Boolean Bit Manipulation Operations BCLR bitaddr Clear direct bit BSET bitaddr Set direct bit BMOV bitaddr, bitaddr Move direct bit to direct bit BMOVN bitaddr, bitaddr...
Page 189 User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Compare and Loop Control Instructions (cont’d) CMPD1 Rw, mem Compare direct word memory to direct GPR and decrement GPR by 1 CMPD2 Rw, #data4 Compare immediate word data to direct GPR and...
Page 190 User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Shift and Rotate Instructions (cont’d) Rw, #data4 Shift right direct word GPR; number of shift cycles specified by immediate data Rw, Rw Rotate left direct word GPR;...
Page 191 User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Data Movement (cont’d) [Rw], mem Move direct word memory to indirect memory mem, [Rw] Move indirect word memory to direct memory reg, mem Move direct word memory to direct register...
Page 192 User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Data Movement (cont’d) MOVBZ Rw, Rb Move direct byte GPR with zero extension to direct word GPR MOVBZ reg, mem Move direct byte memory with zero extension to direct...
Page 193 User’s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Return Operations Return from intra-segment subroutine RETS Return from inter-segment subroutine RETP Return from intra-segment subroutine and pop direct word register from system stack RETI Return from interrupt service subroutine...
Page 194: Instruction Opcodes
User’s Manual C166S V1 SubSystem Instruction Set Instruction Opcodes The following pages list the instructions of the C166S ordered by their hexadecimal opcodes. This helps to identify specific instructions when reading executable code, ie. during the debugging phase. Notes for Opcode Lists 1.
Page 195 User’s Manual C166S V1 SubSystem Instruction Set Hex- Num- Mnemonic Operands Hex- Num- Mnemonic Operands code ber of ber of code Bytes Bytes Rw, Rw Rw, Rw ADDB Rb, Rb SUBB Rb, Rb reg, mem reg, mem ADDB reg, mem...
Page 196 User’s Manual C166S V1 SubSystem Instruction Set Hex- Num- Mnemonic Operands Hex- Num- Mnemonic Operands code ber of code ber of Bytes Bytes Rw, Rw Rw, Rw CMPB Rb, Rb ANDB Rb, Rb reg, mem reg, mem CMPB reg, mem...
Page 197 User’s Manual C166S V1 SubSystem Instruction Set Hex- Num- Mnemonic Operands Hex- Num- Mnemonic Operands code ber of code ber of Bytes Bytes CMPI1 Rw, #data4 CMPD1 Rw, #data4 NEGB CMPI1 Rw, mem CMPD1 Rw, mem CoXXX CoXXX [Rw], mem...
Page 198 User’s Manual C166S V1 SubSystem Instruction Set Hex- Num- Mnemonic Operands Hex- Num- Mnemonic Operands code ber of code ber of Bytes Bytes MOVBZ Rw, Rb Rw, #data4 MOVB Rb, #data4 MOVBZ reg, mem PCALL reg, caddr [Rw+#data16], MOVB [Rw+#data16],...
Page 199: Instruction Description
User’s Manual C166S V1 SubSystem Instruction Set Instruction Description This chapter describes each instruction in details. The instructions are listed alphabetically, and the description contains the following elements. • Instruction Name: Specifies the mnemonic opcode of the instruction in oversized bold lettering for easy reference.
Page 200 User’s Manual C166S V1 SubSystem Instruction Set Monadic operations: operator (opX) ¬ (opX) logically COMPLEMENTED Parentheses indicate a method of the used operand addressing as follows: Specifies the immediate constant value of opX (opX) Specifies the contents of opX (opX[n])
Page 201 User’s Manual C166S V1 SubSystem Instruction Set Only instructions which extend byte data to word change data type. Note that the data types mentioned in this subsection do not cover accesses to indirect address pointers or to the system stack. These accesses are always performed with word data. Moreover, no data type is specified for System Control Instructions and for those of the branch instructions which do not access any explicitly addressed data.
Page 202 User’s Manual C166S V1 SubSystem Instruction Set Condition Test Description Condition Code Code Number c Mnemonic cc cc_SGT (Z∨(N⊕V)) = 0 Signed greater than cc_NET (Z∨E) = 0 Not equal AND not end of table • Condition Flags: This part reflects the state of the N, C, V, Z and E flags in the PSW...
Page 203 User’s Manual C166S V1 SubSystem Instruction Set ’B’ The flag contains the original value of the specified bit operand. ’B’ The flag contains the complemented value of the specified bit operand. Note: If the PSW register was specified as the destination operand of an instruction, the...
Page 204 User’s Manual C166S V1 SubSystem Instruction Set ...#:# : 5-bit immediate constant (#data5) : 4-bit condition code specification (cc) : 4-bit short GPR address (Rwn or Rbn) : 4-bit short GPR address (Rwm or Rbm) : 4-bit position of the source bit within the word specified by QQ...
Page 205 User’s Manual C166S V1 SubSystem Instruction Set N2N1 N4N3 N6N5 N8N7 Representation in the Assembler Listing: High Byte 2nd word Low Byte 2nd word High Byte 1st word Low Byte 1st word Internal Organization: Bits in ascending order LSB Figure 5-1...
Page 206 User’s Manual C166S V1 SubSystem Instruction Set User’s Manual 5-28 V 1.6, 2001-08...
Page 207: Detailed Instruction Set
User’s Manual C166S V1 SubSystem Detailed Instruction Set Detailed Instruction Set The following pages of this section contain a detailed description of each instruction in alphabetical order. User’s Manual V 1.6, 2001-08...
Page 208 User’s Manual C166S V1 SubSystem Detailed Instruction Set Integer Addition Group Arithmetic Instructions Syntax ADD op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) + (op2) Description Performs a 2’s complement binary addition of the source operand specified by op2 and the destination operand specified by op1.
Page 209 User’s Manual C166S V1 SubSystem Detailed Instruction Set ADDB ADDB Integer Addition Group Arithmetic Instructions Syntax ADDB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) + (op2) Description Performs a 2’s complement binary addition of the source operand specified by op2 and the destination operand specified by op1.
Page 210 User’s Manual C166S V1 SubSystem Detailed Instruction Set ADDC ADDC Integer Addition with Carry Group Arithmetic Instructions Syntax ADDC op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) + (op2) + (C) Description Performs a 2’s complement binary addition of the source operand specified by op2, the...
Page 211 User’s Manual C166S V1 SubSystem Detailed Instruction Set ADDCB ADDCB Integer Addition with Carry Group Arithmetic Instructions Syntax ADDCB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) + (op2) + (C) Description Performs a 2’s complement binary addition of the source operand specified by op2, the...
Page 212 User’s Manual C166S V1 SubSystem Detailed Instruction Set Logical AND Group Logical Instructions Syntax AND op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) ∧ (op2) Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1.
Page 213 User’s Manual C166S V1 SubSystem Detailed Instruction Set ANDB ANDB Logical AND Group Logical Instructions Syntax ANDB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) ∧ (op2) Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1.
Page 214 User’s Manual C166S V1 SubSystem Detailed Instruction Set ASHR ASHR Arithmetic Shift Right Group Shift and Rotate Instructions Syntax ASHR op1, op2 op1 → WORD Source Operand(s) op2 → shift counter op1 → WORD Destination Operand(s) Operation (count) ← (op2) (V) ←...
Page 215 User’s Manual C166S V1 SubSystem Detailed Instruction Set Encoding Mnemonic Format Bytes ASHR , #data4 BC #n ASHR , Rw AC nm User’s Manual V 1.6, 2001-08...
Page 216 User’s Manual C166S V1 SubSystem Detailed Instruction Set ATOMIC ATOMIC Begin ATOMIC Sequence Group System Control Instructions Syntax ATOMIC op1 op1 → 2-bit instruction counter Source Operand(s) Destination Operand(s) none Operation (count) ← (op1) [1 ≤ ≤ Disable interrupts and Class A traps DO WHILE ((count) ≠...
Page 217 User’s Manual C166S V1 SubSystem Detailed Instruction Set BAND BAND Bit Logical AND Group Boolean Bit Manipulation Instructions Syntax BAND op1, op2 op1, op2 → BIT Source Operand(s) op1 → BIT Destination Operand(s) Operation (op1) ← (op1) ∧ (op2) Description Performs a single bit logical AND of the source bit specified by op2 and the destination bit specified by op1.
Page 218 User’s Manual C166S V1 SubSystem Detailed Instruction Set BCLR BCLR Bit Clear Group Boolean Bit Manipulation Instructions Syntax BCLR op1 Source Operand(s) none op1 → BIT Destination Operand(s) Operation (op1) ← 0 Description Clears the bit specified by op1. This instruction is primarily used for peripheral and system control.
Page 219 User’s Manual C166S V1 SubSystem Detailed Instruction Set BCMP BCMP Bit to Bit Compare Group Boolean Bit Manipulation Instructions Syntax BCMP op1, op2 op1, op2 → BIT Source Operand(s) Destination Operand(s) none Operation (op1) ⇔ (op2) Description Performs a single bit comparison of the source bit specified by op1 and the source bit specified by op2.
Page 220 User’s Manual C166S V1 SubSystem Detailed Instruction Set BFLDH BFLDH Bit Field High Byte Group Boolean Bit Manipulation Instructions Syntax BFLDH op1, op2, op3 op1 → WORD Source Operand(s) op2, op3 → BYTE op1 → WORD Destination Operand(s) Operation (count) ← 0 DO WHILE ((count) <8)
Page 221 User’s Manual C166S V1 SubSystem Detailed Instruction Set BFLDL BFLDL Bit Field Low Byte Group Boolean Bit Manipulation Instructions Syntax BFLDL op1, op2, op3 op1 → WORD Source Operand(s) op2, op3 → BYTE op1 → WORD Destination Operand(s) Operation (count) ← 0 DO WHILE ((count) <8)
Page 222 User’s Manual C166S V1 SubSystem Detailed Instruction Set BMOV BMOV Bit to Bit Move Group Boolean Bit Manipulation Instructions Syntax BMOV op1, op2 op2 → BIT Source Operand(s) op1 → BIT Destination Operand(s) Operation (op1) ← (op2) Description Moves a single bit from the source operand specified by op2 into the destination operand specified by op1.
Page 223 User’s Manual C166S V1 SubSystem Detailed Instruction Set BMOVN BMOVN Bit to Bit Move and Negate Group Boolean Bit Manipulation Instructions Syntax BMOVN op1, op2 op2 → BIT Source Operand(s) op1 → BIT Destination Operand(s) Operation (op1) ← ¬(op2) Description Moves the complement of a single bit from the source operand specified by op2 into the destination operand specified by op1.
Page 224 User’s Manual C166S V1 SubSystem Detailed Instruction Set Bit Logical OR Group Boolean Bit Manipulation Instructions Syntax BOR op1, op2 op1, op2 → BIT Source Operand(s) op1 → BIT Destination Operand(s) Operation (op1) ← (op1) ∨ (op2) Description Performs a single bit logical OR of the source bit specified by op2 and the destination bit specified by op1.
Page 225 User’s Manual C166S V1 SubSystem Detailed Instruction Set BSET BSET Bit Set Group Boolean Bit Manipulation Instructions Syntax BSET op1 Source Operand(s) none op1 → BIT Destination Operand(s) Operation (op1) ← 1 Description Sets the bit specified by op1. CPU Flags Always cleared.
Page 226 User’s Manual C166S V1 SubSystem Detailed Instruction Set BXOR BXOR Bit Logical XOR Group Boolean Bit Manipulation Instructions Syntax BXOR op1, op2 op1, op2 → BIT Source Operand(s) op1 → BIT Destination Operand(s) Operation (op1) ← (op1) ⊕ (op2) Description Performs a single bit logical EXCLUSIVE OR of the source bit specified by op2 and the destination bit specified by op1.
Page 227 User’s Manual C166S V1 SubSystem Detailed Instruction Set CALLA CALLA Call Subroutine Absolute Group Call Instructions Syntax CALLA op1, op2 op1 → extended condition code Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation IF (op1) THEN (SP) ← (SP) - 2 ((SP)) ←...
Page 228 User’s Manual C166S V1 SubSystem Detailed Instruction Set CALLI CALLI Call Subroutine Indirect Group Call Instructions Syntax CALLI op1, op2 op1 → condition code Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation IF (op1) THEN (SP) ← (SP) - 2 ((SP)) ←...
Page 229 User’s Manual C166S V1 SubSystem Detailed Instruction Set CALLR CALLR Call Subroutine Relative Group Call Instructions Syntax CALLR op1 op1 → 8-bit signed displacement Source Operand(s) Destination Operand(s) none Operation (SP) ← (SP) - 2 ((SP)) ← (IP) (IP) ← (IP) + 2*sign_extend(op1)
Page 230 User’s Manual C166S V1 SubSystem Detailed Instruction Set CALLS CALLS Call Inter-Segment Subroutine Group Call Instructions Syntax CALLS op1, op2 op1 → segment number Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation (SP) ← (SP) - 2 ((SP)) ←...
Page 231 User’s Manual C166S V1 SubSystem Detailed Instruction Set Integer Compare Group Boolean Bit Manipulation Instructions Syntax CMP op1, op2 op1, op2 → WORD Source Operand(s) Destination Operand(s) none Operation (op1) ⇔ (op2) Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2’s complement binary subtraction of op2 from op1.
Page 232 User’s Manual C166S V1 SubSystem Detailed Instruction Set CMPB CMPB Integer Compare Group Boolean Bit Manipulation Instructions Syntax CMPB op1, op2 op1, op2 → BYTE Source Operand(s) Destination Operand(s) none Operation (op1) ⇔ (op2) Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2’s complement binary subtraction of op2 from op1.
Page 233 User’s Manual C166S V1 SubSystem Detailed Instruction Set CMPD1 CMPD1 Integer Compare and Decrement by 1 Group Compare and Loop Control Instructions Syntax CMPD1 op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ⇔ (op2) (op1) ←...
Page 234 User’s Manual C166S V1 SubSystem Detailed Instruction Set CMPD2 CMPD2 Integer Compare and Decrement by 2 Group Compare and Loop Control Instructions Syntax CMPD2 op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ⇔ (op2) (op1) ←...
Page 235 User’s Manual C166S V1 SubSystem Detailed Instruction Set CMPI1 CMPI1 Integer Compare and Increment by 1 Group Compare and Loop Control Instructions Syntax CMPI1 op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ⇔ (op2) (op1) ←...
Page 236 User’s Manual C166S V1 SubSystem Detailed Instruction Set CMPI2 CMPI2 Integer Compare and Increment by 2 Group Compare and Loop Control Instructions Syntax CMPI2 op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ⇔ (op2) (op1) ←...
Page 237 User’s Manual C166S V1 SubSystem Detailed Instruction Set Integer One’s Complement Group Arithmetic Instructions Syntax CPL op1 op1 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← ¬(op1) Description Performs a 1’s complement of the source operand specified by op1. The result is stored back into op1.
Page 238 User’s Manual C166S V1 SubSystem Detailed Instruction Set CPLB CPLB Integer One’s Complement Group Arithmetic Instructions Syntax CPLB op1 op1 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← ¬(op1) Description Performs a 1’s complement of the source operand specified by op1. The result is stored back into op1.
Page 239 User’s Manual C166S V1 SubSystem Detailed Instruction Set DISWDT DISWDT Disable Watchdog Timer Group System Control Instructions Syntax DISWDT Source Operand(s) none Destination Operand(s) none Operation Disable the watchdog timer Description This instruction disables the watchdog timer. If the WDTCTL bit is cleared, the DISWDT instruction can be executed at any time between the Reset and the first execution of either EINIT or SRVWDT.
Page 240 User’s Manual C166S V1 SubSystem Detailed Instruction Set 16-by-16 Signed Division Group Arithmetic Instructions Syntax DIV op1 op1 → WORD Source Operand(s) MDL → WORD MD → DOUBLEWORD Destination Operand(s) Operation (MDL) ← (MDL) / (op1) (MDH) ← (MDL) mod (op1)
Page 241 User’s Manual C166S V1 SubSystem Detailed Instruction Set DIVL DIVL 32-by-16 Signed Division Group Arithmetic Instructions Syntax DIVL op1 op1 → WORD Source Operand(s) MD → DOUBLEWORD MD → DOUBLEWORD Destination Operand(s) Operation (MDL) ← (MD) / (op1) (MDH) ← (MD) mod (op1)
Page 242 User’s Manual C166S V1 SubSystem Detailed Instruction Set DIVLU DIVLU 32-by-16 Unsigned Division Group Arithmetic Instructions Syntax DIVLU op1 op1 → WORD Source Operand(s) MD → DOUBLEWORD MD → DOUBLEWORD Destination Operand(s) Operation (MDL) ← (MD) / op1 (MDH) ← (MD) mod (op1)
Page 243 User’s Manual C166S V1 SubSystem Detailed Instruction Set DIVU DIVU 16-by-16 Unsigned Division Group Arithmetic Instructions Syntax DIVU op1 op1 → WORD Source Operand(s) MDL → WORD MD → DOUBLEWORD Destination Operand(s) Operation (MDL) ← (MDL) / (op1) (MDH) ← (MDL) mod (op1)
Page 244 User’s Manual C166S V1 SubSystem Detailed Instruction Set EINIT EINIT End of Initialization Group System Control Instructions Syntax EINIT Source Operand(s) none Destination Operand(s) none Operation End of Initialization Description After a reset, the reset output pin RSTOUT is pulled low. It remains low until the EINIT instruction has been executed at which time it goes high.
Page 245 User’s Manual C166S V1 SubSystem Detailed Instruction Set EXTP EXTP Begin EXTended Page Sequence Group System Control Instructions Syntax EXTP op1, op2 op1 → 10-bit page number Source Operand(s) op2 → 2-bit instruction counter Destination Operand(s) none Operation (count) ← (op2) [1 ≤ op2 ≤ 4] Disable interrupts and Class A traps Data_Page ←...
Page 246 User’s Manual C166S V1 SubSystem Detailed Instruction Set Encoding Mnemonic Format Bytes EXTP #pag , #irang2 D7 :01##-0 pp 0:00pp EXTP , #irang2 DC :01##-m User’s Manual 6-40 V 1.6, 2001-08...
Page 247 User’s Manual C166S V1 SubSystem Detailed Instruction Set EXTPR EXTPR Begin EXTended Page and Register Sequence Group System Control Instructions Syntax EXTPR op1, op2 op1 → 10-bit page number Source Operand(s) op2 → 2-bit instruction counter Destination Operand(s) none Operation (count) ←...
Page 248 User’s Manual C166S V1 SubSystem Detailed Instruction Set Not affected. Not affected. Encoding Mnemonic Format Bytes EXTPR #pag , #irang2 D7 :11##-0 pp 0:00pp EXTPR , #irang2 DC :11##-m User’s Manual 6-42 V 1.6, 2001-08...
Page 249 User’s Manual C166S V1 SubSystem Detailed Instruction Set EXTR EXTR Begin EXTended Register Sequence Group System Control Instructions Syntax EXTR op1 op1 → 2-bit instruction counter Source Operand(s) Destination Operand(s) none Operation (count) ← (op1) [1 ≤ op1 ≤ 4] Disable interrupts and Class A traps SFR_range ←...
Page 250 User’s Manual C166S V1 SubSystem Detailed Instruction Set EXTS EXTS Begin EXTended Segment Sequence Group System Control Instructions Syntax EXTS op1, op2 op1 → segment number Source Operand(s) op2 → 2-bit instruction counter Destination Operand(s) none Operation (count) ← (op2) [1 ≤...
Page 251 User’s Manual C166S V1 SubSystem Detailed Instruction Set Encoding Mnemonic Format Bytes EXTS #seg , #irang2 D7 :00##-0 ss 00 EXTS , #irang2 DC :00##-m User’s Manual 6-45 V 1.6, 2001-08...
Page 252 User’s Manual C166S V1 SubSystem Detailed Instruction Set EXTSR EXTSR Begin EXTended Segment and Register Sequence Group System Control Instructions Syntax EXTSR op1, op2 op1 → segment number Source Operand(s) op2 → 2-bit instruction counter Destination Operand(s) none Operation (count) ← (op2) [1 ≤ op2 ≤ 4] Disable interrupts and Class A traps Data_Segment ←...
Page 253 User’s Manual C166S V1 SubSystem Detailed Instruction Set Not affected. Not affected. Not affected. Encoding Mnemonic Format Bytes EXTSR #seg , #irang2 D7 :10##-0 ss 00 EXTSR , #irang2 DC :10##-m User’s Manual 6-47 V 1.6, 2001-08...
Page 254 User’s Manual C166S V1 SubSystem Detailed Instruction Set IDLE IDLE Enter Idle Mode Group System Control Instructions Syntax IDLE Source Operand(s) none Destination Operand(s) none Operation Enter Idle Mode Description This instruction causes the part to enter the idle mode. In this mode, the CPU is powered down while the peripherals remain running.
Page 255 User’s Manual C166S V1 SubSystem Detailed Instruction Set Relative Jump if Bit Set Group Jump Instructions Syntax JB op1, op2 op1 → BIT Source Operand(s) op2 → 8-bit signed displacement Destination Operand(s) none Operation IF ((op1) = 1) THEN (IP) ← (IP) + 2*sign_extend(op2)
Page 256 User’s Manual C166S V1 SubSystem Detailed Instruction Set Relative Jump if Bit Set and Clear Bit Group Jump Instructions Syntax JBC op1, op2 op1 → BIT Source Operand(s) op2 → 8-bit signed displacement Destination Operand(s) none Operation IF ((op1) = 1) THEN (op1) ←...
Page 257 User’s Manual C166S V1 SubSystem Detailed Instruction Set Encoding Mnemonic Format Bytes bitaddr , rel AA QQ rr q0 User’s Manual 6-51 V 1.6, 2001-08...
Page 258 User’s Manual C166S V1 SubSystem Detailed Instruction Set JMPA JMPA Absolute Conditional Jump Group Jump Instructions Syntax JMPA op1, op2 op1 → extended condition code Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation IF ((op1) = 1) THEN (IP) ←...
Page 259 User’s Manual C166S V1 SubSystem Detailed Instruction Set JMPI JMPI Indirect Conditional Jump Group Jump Instructions Syntax JMPI op1, op2 op1 → condition code Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation IF ((op1) = 1) THEN (IP) ←...
Page 260 User’s Manual C166S V1 SubSystem Detailed Instruction Set JMPR JMPR Relative Conditional Jump Group Jump Instructions Syntax JMPR op1, op2 op1 → condition code Source Operand(s) op2 → 8-bit signed displacement Destination Operand(s) none Operation IF ((op1) = 1) THEN (IP) ←...
Page 261 User’s Manual C166S V1 SubSystem Detailed Instruction Set JMPS JMPS Absolute Inter-Segment Jump Group Jump Instructions Syntax JMPS op1, op2 op1 → segment number Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation (CSP) ← op1 (IP) ← op2...
Page 262 User’s Manual C166S V1 SubSystem Detailed Instruction Set Relative Jump if Bit Clear Group Jump Instructions Syntax JNB op1, op2 op1 → BIT Source Operand(s) op2 → 8-bit signed displacement Destination Operand(s) none Operation IF ((op1) = 0) THEN (IP) ← (IP) + 2*sign_extend(op2)
Page 263 User’s Manual C166S V1 SubSystem Detailed Instruction Set JNBS JNBS Relative Jump if Bit Clear and Set Bit Group Jump Instructions Syntax JNBS op1, op2 op1 → BIT Source Operand(s) op2 → 8-bit signed displacement Destination Operand(s) none Operation IF ((op1) = 0) THEN (op1) ←...
Page 264 User’s Manual C166S V1 SubSystem Detailed Instruction Set Move Data Group Data Movement Instructions Syntax MOV op1, op2 op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op2) Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1.
Page 265 User’s Manual C166S V1 SubSystem Detailed Instruction Set ] , Rw B8 nm +] , [Rw D8 nm ] , [Rw E8 nm ] , [Rw C8 nm ] , mem 84 0n MM MM mem , [Rw 94 0n MM MM...
Page 266 User’s Manual C166S V1 SubSystem Detailed Instruction Set MOVB MOVB Move Data Group Data Movement Instructions Syntax MOVB op1, op2 op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op2) Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1.
Page 267 User’s Manual C166S V1 SubSystem Detailed Instruction Set MOVB ] , Rb B9 nm MOVB +] , [Rw D9 nm MOVB ] , [Rw E9 nm MOVB ] , [Rw C9 nm MOVB ] , mem A4 0n MM MM...
Page 268 User’s Manual C166S V1 SubSystem Detailed Instruction Set MOVBS MOVBS Move Byte Sign Extend Group Data Movement Instructions Syntax MOVBS op1, op2 op2 → BYTE Source Operand(s) op1 → WORD Destination Operand(s) Operation (low byte op1) ← (op2) IF ((op2[7]) = 1) THEN (high byte op1) ←...
Page 269 User’s Manual C166S V1 SubSystem Detailed Instruction Set MOVBZ MOVBZ Move Byte Zero Extend Group Data Movement Instructions Syntax MOVBZ op1, op2 op2 → BYTE Source Operand(s) op1 → WORD Destination Operand(s) Operation (low byte op1) ← (op2) (high byte op1) ← 00H...
Page 270 User’s Manual C166S V1 SubSystem Detailed Instruction Set Signed Multiplication Group Arithmetic Instructions Syntax MUL op1, op2 op1, op2 → WORD Source Operand(s) MD → DOUBLEWORD Destination Operand(s) Operation (MD) ← (op1) * (op2) Description Performs a 16-bit by 16-bit signed multiplication using the two words specified by operands op1 and op2 respectively.
Page 271 User’s Manual C166S V1 SubSystem Detailed Instruction Set MULU MULU Unsigned Multiplication Group Arithmetic Instructions Syntax MULU op1, op2 op1, op2 → WORD Source Operand(s) MD → DOUBLEWORD Destination Operand(s) Operation (MD) ← (op1) * (op2) Description Performs a 16-bit by 16-bit unsigned multiplication using the two words specified by operands op1 and op2 respectively.
Page 272 User’s Manual C166S V1 SubSystem Detailed Instruction Set Integer Two’s Complement Group Arithmetic Instructions Syntax NEG op1 op1 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← 0 - (op1) Description Performs a binary 2’s complement of the source operand specified by op1. The result is then stored in op1.
Page 273 User’s Manual C166S V1 SubSystem Detailed Instruction Set NEGB NEGB Integer Two’s Complement Group Arithmetic Instructions Syntax NEGB op1 op1 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← 0 - (op1) Description Performs a binary 2’s complement of the source operand specified by op1. The result is then stored in op1.
Page 274 User’s Manual C166S V1 SubSystem Detailed Instruction Set No Operation Group Null operation Syntax Source Operand(s) none Destination Operand(s) none Operation No Operation Description This instruction causes a null operation to be performed. A null operation causes no change in the status of the flags.
Page 275 User’s Manual C166S V1 SubSystem Detailed Instruction Set Logical OR Group Logical Instructions Syntax OR op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) ∨ (op2) Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1.
Page 276 User’s Manual C166S V1 SubSystem Detailed Instruction Set Logical OR Group Logical Instructions Syntax ORB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) ∨ (op2) Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1.
Page 277 User’s Manual C166S V1 SubSystem Detailed Instruction Set PCALL PCALL Push Word and Call Subroutine Absolute Group Call Instructions Syntax PCALL op1, op2 op1 → WORD Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation (tmp) ← (op1) (SP) ←...
Page 278 User’s Manual C166S V1 SubSystem Detailed Instruction Set Encoding Mnemonic Format Bytes PCALL reg , caddr E2 RR MM MM User’s Manual 6-72 V 1.6, 2001-08...
Page 279 User’s Manual C166S V1 SubSystem Detailed Instruction Set Pop Word from System Stack Group System Stack Instructions Syntax POP op1 Source Operand(s) none op1 → WORD Destination Operand(s) Operation (tmp) ← ((SP)) (SP) ← (SP) + 2 (op1) ← (tmp)
Page 280 User’s Manual C166S V1 SubSystem Detailed Instruction Set PRIOR PRIOR Prioritize Register Group Prioritize Instruction Syntax PRIOR op1, op2 op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (tmp) ← (op2) (count) ← 0 DO WHILE (((tmp[15]) ≠ 1) AND ((op2) ≠ 0))) (tmp[n]) ←...
Page 281 User’s Manual C166S V1 SubSystem Detailed Instruction Set PUSH PUSH Push Word on System Stack Group System Stack Instructions Syntax PUSH op1 op1 → WORD Source Operand(s) Destination Operand(s) none Operation (tmp) ← (op1) (SP) ← (SP) - 2 ((SP)) ← (tmp)
Page 282 User’s Manual C166S V1 SubSystem Detailed Instruction Set PWRDN PWRDN Enter Power Down Mode Group System Control Instructions Syntax PWRDN Source Operand(s) none Destination Operand(s) none Operation Enter Power Down Mode Description This instruction causes the part to enter the power down mode. In this mode, all peripherals and the CPU are powered down until the part is externally reset.
Page 283 User’s Manual C166S V1 SubSystem Detailed Instruction Set Return from Subroutine Group Return Instructions Syntax Source Operand(s) none Destination Operand(s) none Operation (IP) ← ((SP)) (SP) ← (SP) + 2 Description Returns from a subroutine. The IP is popped from the system stack.
Page 284 User’s Manual C166S V1 SubSystem Detailed Instruction Set RETI RETI Return from Interrupt Subroutine Group Return Instructions Syntax RETI Source Operand(s) none Destination Operand(s) none Operation (IP) ← ((SP)) (SP) ← (SP) + 2 IF (SYSCON.SGTDIS = 0) THEN (CSP) ← ((SP)) (SP) ←...
Page 285 User’s Manual C166S V1 SubSystem Detailed Instruction Set RETP RETP Return from Subroutine and Pop Word Group Return Instructions Syntax RETP op1 Source Operand(s) none op1 → WORD Destination Operand(s) Operation (IP) ← ((SP)) (SP) ← (SP) + 2 (tmp) ← ((SP)) (SP) ←...
Page 286 User’s Manual C166S V1 SubSystem Detailed Instruction Set RETS RETS Return from Inter-Segment Subroutine Group Return Instructions Syntax RETS Source Operand(s) none Destination Operand(s) none Operation (IP) ← ((SP)) (SP) ← (SP) + 2 (CSP) ← ((SP)) (SP) ← (SP) + 2 Description Returns from an inter-segment subroutine.
Page 287 User’s Manual C166S V1 SubSystem Detailed Instruction Set Rotate Left Group Shift and Rotate Instructions Syntax ROL op1, op2 op1 → WORD Source Operand(s) op2 → shift counter op1 → WORD Destination Operand(s) Operation (count) ← (op2) (C) ← 0 DO WHILE ((count) ≠...
Page 288 User’s Manual C166S V1 SubSystem Detailed Instruction Set Encoding Mnemonic Format Bytes , #data4 1C #n , Rw 0C nm User’s Manual 6-82 V 1.6, 2001-08...
Page 289 User’s Manual C166S V1 SubSystem Detailed Instruction Set Rotate Right Group Shift and Rotate Instructions Syntax ROR op1, op2 op1 → WORD Source Operand(s) op2 → shift counter op1 → WORD Destination Operand(s) Operation (count) ← (op2) (C) ← 0 (V) ←...
Page 290 User’s Manual C166S V1 SubSystem Detailed Instruction Set Encoding Mnemonic Format Bytes , #data4 3C #n , Rw 2C nm User’s Manual 6-84 V 1.6, 2001-08...
Page 291 User’s Manual C166S V1 SubSystem Detailed Instruction Set SCXT SCXT Switch Context Group System Stack Instructions Syntax SCXT op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (tmp1) ← (op1) (tmp2) ← (op2) (SP) ← (SP) - 2 ((SP)) ←...
Page 292 User’s Manual C166S V1 SubSystem Detailed Instruction Set Shift Left Group Shift and Rotate Instructions Syntax SHL op1, op2 op1 → WORD Source Operand(s) op2 → shift counter op1 → WORD Destination Operand(s) Operation (count) ← (op2) (C) ← 0 DO WHILE ((count) ≠...
Page 293 User’s Manual C166S V1 SubSystem Detailed Instruction Set Encoding Mnemonic Format Bytes , #data4 5C #n , Rw 4C nm User’s Manual 6-87 V 1.6, 2001-08...
Page 294 User’s Manual C166S V1 SubSystem Detailed Instruction Set Shift Right Group Shift and Rotate Instructions Syntax SHR op1, op2 op1 → WORD Source Operand(s) op2 → shift counter op1 → WORD Destination Operand(s) Operation (count) ← (op2) (C) ← 0 (V) ←...
Page 295 User’s Manual C166S V1 SubSystem Detailed Instruction Set The carry flag is set according to the last least significant bit shifted out of op1. Cleared for a shift count of zero. Set if the most significant bit of the result is set. Cleared otherwise.
Page 296 User’s Manual C166S V1 SubSystem Detailed Instruction Set SRST SRST Software Reset Group System Control Instructions Syntax SRST Source Operand(s) none Destination Operand(s) none Operation Software Reset Description This instruction is used to perform a software reset. A software reset has the same effect on the microcontroller as an externally applied hardware reset.
Page 297 User’s Manual C166S V1 SubSystem Detailed Instruction Set SRVWDT SRVWDT Service Watchdog Timer Group System Control Instructions Syntax SRVWDT Source Operand(s) none Destination Operand(s) none Operation Service Watchdog Timer Description This instruction reloads the high order byte of the Watchdog Timer with a preset value and clears the low byte.
Page 298 User’s Manual C166S V1 SubSystem Detailed Instruction Set Integer Subtraction Group Arithmetic Instructions Syntax SUB op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) - (op2) Description Performs a 2’s complement binary subtraction of the source operand specified by op2 and the destination operand specified by op1.
Page 299 User’s Manual C166S V1 SubSystem Detailed Instruction Set SUBB SUBB Integer Subtraction Group Arithmetic Instructions Syntax SUBB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) - (op2) Description Performs a 2’s complement binary subtraction of the source operand specified by op2 and the destination operand specified by op1.
Page 300 User’s Manual C166S V1 SubSystem Detailed Instruction Set SUBC SUBC Integer Subtraction with Carry Group Arithmetic Instructions Syntax SUBC op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) - (op2) - (C) Description Performs a 2’s complement binary subtraction of the source operand specified by op2...
Page 301 User’s Manual C166S V1 SubSystem Detailed Instruction Set SUBCB SUBCB Integer Subtraction with Carry Group Arithmetic Instructions Syntax SUBCB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) - (op2) - (C) Description Performs a 2’s complement binary subtraction of the source operand specified by op2...
Page 302 User’s Manual C166S V1 SubSystem Detailed Instruction Set TRAP TRAP Software Trap Group Call Instructions Syntax TRAP op1 op1 → 7-bit trap number Source Operand(s) Destination Operand(s) none Operation (SP) ← (SP) - 2 ((SP) ← (PSW) IF (SYSCON.SGTDIS = 0) THEN (SP) ←...
Page 303 User’s Manual C166S V1 SubSystem Detailed Instruction Set Encoding Mnemonic Format Bytes TRAP #trap7 9B t:ttt0 User’s Manual 6-97 V 1.6, 2001-08...
Page 304 User’s Manual C166S V1 SubSystem Detailed Instruction Set Logical Exclusive OR Group Logical Instructions Syntax XOR op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) ⊕ (op2) Description Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1.
Page 305 User’s Manual C166S V1 SubSystem Detailed Instruction Set XORB XORB Logical Exclusive OR Group Logical Instructions Syntax XORB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) ⊕ (op2) Description Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1.
Page 306 User’s Manual C166S V1 SubSystem Detailed Instruction Set User’s Manual 6-100 V 1.6, 2001-08...
Page 307 User’s Manual C166S V1 SubSystem Parallel Ports Parallel Ports In order to accept or generate single external control signals or parallel data, the C166S s provides up to 48 parallel IO lines organized into six 8-bit IO ports (PORT0 made of P0H and P0L, PORT1 made of P1H and P1L, Port 4, Port 6).
Page 308: Alternate Port Functions
User’s Manual C166S V1 SubSystem Parallel Ports Alternate Port Functions In order to provide a maximum of flexibility for different applications and their specific IO requirements port lines have programmable alternate input or output functions associated with them. Table 7-1...
Page 309 User’s Manual C166S V1 SubSystem Parallel Ports way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode. All port lines that are not used for these alternate functions may be used as general purpose IO lines.
Page 310 User’s Manual C166S V1 SubSystem Parallel Ports PORT0 High Register SFR (FF02 Reset value: - - 00 Function P0X.y Port data register P0H or P0L bit y DP0L P0L Direction Ctrl. Register ESFR (F100 Reset value: - - 00 DP0L...
Page 311 User’s Manual C166S V1 SubSystem Parallel Ports During external accesses in demultiplexed bus modes PORT0 reads the incoming instruction or data word or outputs the data byte or word. Alternate Function P0H.7 AD15 P0H.6 AD14 P0H.5 AD13 P0H.4 AD12 P0H.3 AD11 P0H.2...
Page 312 User’s Manual C166S V1 SubSystem Parallel Ports The figure below shows the structure of a PORT0 pin. Internal Bus Port Output Direction Register Register AltDir AltEN AltDataOut Driver Clock AltDataIn Input Register P0H.7-0, P0L.7-0 Figure 7-3 Block Diagram of a PORT0 Pin User’s Manual...
Page 313 User’s Manual C166S V1 SubSystem Parallel Ports PORT1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halfs of PORT1 can be written (e.g. via a PEC transfer) without effecting the other half.
Page 314 User’s Manual C166S V1 SubSystem Parallel Ports Function DP1X.y Port direction register DP1H or DP1L bit y DP1X.y = 0: Port line P1X.y is an input (high-impedance) DP1X.y = 1: Port line P1X.y is an output Alternate Functions of PORT1 When a demultiplexed external bus is enabled, PORT1 is used as address bus.
Page 315 User’s Manual C166S V1 SubSystem Parallel Ports The figures below show the structure of PORT1 pins. The upper 4 pins of PORT1 combine internal bus data and alternate data output before the port register input. Internal Bus Port Output Direction...
Page 316 User’s Manual C166S V1 SubSystem Parallel Ports Port 4 If this 8-bit port is used for general purpose IO, the direction of each line can be configured via the corresponding direction register DP4. 3RUW 'DWD 5HJLVWHU SFR (FFC8 Reset Value: - - 00 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0...
Page 317 User’s Manual C166S V1 SubSystem Parallel Ports The table below summarizes the alternate functions of Port 4 depending on the number of selected segment address lines. Table 7-2 Alternate Functions of Port 4 Port 4 Std. Function Altern. Function Altern. Function Altern.
Page 318 User’s Manual C166S V1 SubSystem Parallel Ports Internal Bus Port Output Direction Register Register AltDir = ’1’ AltEN AltDataOut Driver Clock AltDataIn Input Register P4.7-0 Figure 7-7 Block Diagram of a Port 4 Pin User’s Manual 7-12 V 1.6, 2001-08...
Page 319 User’s Manual C166S V1 SubSystem Parallel Ports Port 6 If this 8-bit port is used for general purpose IO, the direction of each line can be configured via the corresponding direction register DP6. 3RUW 'DWD 5HJLVWHU SFR (FFCC Reset Value: - - 00 P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0...
Page 320 User’s Manual C166S V1 SubSystem Parallel Ports The table below summarizes the alternate functions of Port 6 depending on the number of selected chip select lines (coded via bitfield CSSEL). Table 7-3 Alternate Functions of Port 6 Port 6 Pin Altern. Function Altern.
Page 321 User’s Manual C166S V1 SubSystem Parallel Ports Internal Bus Port Output Direction Register Register AltDir = ’1’ AltEN AltDataOut Driver Clock AltDataIn Input Register P6.4-0 Figure 7-9 Block Diagram of Port 6 Pins with an alternate output function User’s Manual 7-15 V 1.6, 2001-08...
Page 322 User’s Manual C166S V1 SubSystem Parallel Ports Internal Bus Port Output Direction Register Register Driver Clock Input Register P6.7-5 Figure 7-10 Block Diagram of Port 6 Pins without an alternate output function User’s Manual 7-16 V 1.6, 2001-08...
Page 323: The External Bus Interface
User’s Manual C166S V1 SubSystem The External Bus Interface The External Bus Interface Although the C166S subsystem supports a powerful set of on-chip peripherals and on- chip RAM and ROM/OTP/Flash areas, these internal units cover only a small fraction of the chip’s address space (up to 16 MBytes).
Page 324: Single-Chip Mode
User’s Manual C166S V1 SubSystem The External Bus Interface Single-chip Mode Single-chip mode is entered when the signal conf_start_external_n_i is high during reset. In this case, BUSCON0 is initialized with 0000 , which also resets bit BUSACT0, so no external bus is enabled.
Page 325: Multiplexed Bus Modes
User’s Manual C166S V1 SubSystem The External Bus Interface functions are selected during reset via bitfields SALSEL and CSSEL of register RP0H, respectively. 8.2.1 Multiplexed Bus Modes In the multiplexed bus modes, the 16-bit intra-segment address and the data both use PORT0.
Page 326 User’s Manual C166S V1 SubSystem The External Bus Interface CLKOUT Normal ALE Cycle Normal ALE Extended ALE Cycle Extend. ALE CSxL A23-A0, Valid BHE, CSxE WRL, WRH, WR, WRCS D15-D0 Low Address Data Out (Norm. ALE) D15-D0 Low Address Data Out (Extd.
Page 327 User’s Manual C166S V1 SubSystem The External Bus Interface CLKOUT Normal ALE Cycle Normal ALE Extended ALE Cycle Extend. ALE CSxL A23-A0, Valid BHE, CSxE RDCS D15-D0 Low Address Data In (Norm. ALE) D15-D0 Low Address Data In (Extd. ALE) Section 8.3.4...
Page 328: Demultiplexed Bus Modes
User’s Manual C166S V1 SubSystem The External Bus Interface 8.2.2 Demultiplexed Bus Modes In the demultiplexed bus modes, the 16-bit intra-segment address is permanently output on PORT1, while the data uses PORT0 (16-bit data) or P0L (8-bit data). The upper address lines are permanently output on Port 4 (if selected via SALSEL during reset).
Page 329 User’s Manual C166S V1 SubSystem The External Bus Interface CLKOUT Normal ALE Cycle Normal ALE Extended ALE Cycle Extend. ALE CSxL A23-A0, Valid BHE, CSxE WRL, WRH, WR, WRCS D15-D0 Data Out (Normal Wr.) D15-D0 Data Out (Early Write) Section 8.3.4 Read/Write Delay Section 8.3.5...
Page 330 User’s Manual C166S V1 SubSystem The External Bus Interface CLKOUT Normal ALE Cycle Normal ALE Extended ALE Cycle Extend. ALE CSxL A23-A0, Valid BHE, CSxE RDCS D15-D0 Data In Section 8.3.4 Read/Write Delay MCTC MTTC Section 8.3.2 Memory Cycle Time Section 8.3.3...
Page 331: Switching Among The Bus Modes
User’s Manual C166S V1 SubSystem The External Bus Interface 8.2.3 Switching Among the Bus Modes The EBC allows dynamic switching among different bus modes, i.e., subsequent external bus cycles may be executed in different ways. Certain address areas may use an 8-bit or 16-bit data bus, or predefined waitstates.
Page 332 User’s Manual C166S V1 SubSystem The External Bus Interface This extra time is required to allow the previously-selected device (via demultiplexed bus) to release the data bus, which would be available in a demultiplexed bus cycle. GHPX[HG LGOH PX[HG A23-A0...
Page 333 User’s Manual C166S V1 SubSystem The External Bus Interface External Data Bus Width The EBC can operate on 8-bit- or 16-bit-wide external memory/peripherals. A 16-bit data bus uses PORT0, while an 8-bit data bus only uses P0L, the lower byte of PORT0. This saves on address latches, bus transceivers, bus routing, and memory-related increases in transfer time.
Page 334 User’s Manual C166S V1 SubSystem The External Bus Interface Disable/Enable Control for Pin BHE (BYTDIS) Bit BYTDIS is provided for controlling the active low Byte High Enable (BHE) pin. The function of the BHE pin is enabled if the BYTDIS bit contains a 0. Otherwise, it is disabled and the pin can be used as a standard I/O pin.
Page 335 User’s Manual C166S V1 SubSystem The External Bus Interface CS Signal Generation During external accesses, the EBC can generate a (programmable) number of CS lines on Port 4, which make it possible to select external peripherals or memory banks directly without requiring an external decoder.
Page 336 User’s Manual C166S V1 SubSystem The External Bus Interface Read or Write Chip-Select (CS is renamed WRCS or RDCS in the protocol diagrams) signals remain active only as long as the associated control signal (RD or WR) is active. This also includes the programmable read/write delay. Read chip select is activated only for read cycles;...
Page 337 User’s Manual C166S V1 SubSystem The External Bus Interface CLKOUT Normal ALE Cycle Normal ALE Extended ALE Cycle Extend. ALE CSxL CSxE Valid Section 8.3.1 ALE Length Control Figure 8-7 Latched and Early Chip Select Segment Address versus Chip Select The external bus interface of the C166S supports many configurations for the external memory.
Page 338: Programmable Bus Characteristics
User’s Manual C166S V1 SubSystem The External Bus Interface Programmable Bus Characteristics Important timing characteristics of the external bus interface have been made user- programmable to adapt it to a wide range of external bus and memory configurations with different types of memories and/or peripherals.
Page 339: Programmable Memory Cycle Time
User’s Manual C166S V1 SubSystem The External Bus Interface external bus cycles accessing the appropriate address window will have their ALE signal prolonged by half a CPU clock (1 TCL). Also the address hold time after the falling edge of ALE (on a multiplexed bus) will be prolonged by half a CPU clock, so the data transfer within a bus cycle refers to the same CLKOUT edges as usual (i.e., the data transfer is...
Page 340: Read/Write Signal Delay
User’s Manual C166S V1 SubSystem The External Bus Interface 8.3.4 Read/Write Signal Delay The C166S allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals. The read/write delay controls the time between the falling edge of ALE and the falling edge of the command.
Page 341 User’s Manual C166S V1 SubSystem The External Bus Interface READY-WS MUX/MTTC Running Cycle CLKOUT Command (RD, WR) Asynch. READY Figure 8-9 READY Controlled Bus Cycles Section 8.3.4 Read/Write Delay Section 8.3.5 Early Write Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
Page 342 User’s Manual C166S V1 SubSystem The External Bus Interface Combining the READY function with predefined waitstates is advantageous in two cases: Memory components with a fixed access time and peripherals operating with READY may be grouped into the same address window. The (external) waitstate control logic in this case would activate READY either upon the memory’s chip select or with the...
Page 343: Controlling The External Bus Controller
User’s Manual C166S V1 SubSystem The External Bus Interface Controlling the External Bus Controller A set of registers controls the functions of the EBC. General features such as the usage of interface pins (WR, BHE), segmentation, and internal memory mapping are controlled via register SYSCON.
Page 344 User’s Manual C166S V1 SubSystem The External Bus Interface Field Bits Type Description CSCFG Chip Select Configuration Control Latched CS mode. The CS signals are latched internally and driven to the (enabled) port pins synchronously. Unlatched CS mode. The CS signals are directly derived from the address and driven to the (enabled) port pins.
Page 345 User’s Manual C166S V1 SubSystem The External Bus Interface Field Bits Type Description ROMS1 CPU Configuration Bit Internal Local Memory Mapping Internal Local Memory area mapped to segment 0 (00’0000 ...00’7FFF Internal Local Memory area mapped to segment 1 (01’0000H...01’7FFFH)
Page 346 User’s Manual C166S V1 SubSystem The External Bus Interface BUSCON0 Bus Control Register 0 SFR (FF0C Reset value: 0XX0 BTYP MCTC BUSCON1 Bus Control Register 1 SFR (FF14 Reset value: 0000 BTYP MCTC BUSCON2 Bus Control Register 2 SFR (FF16...
Page 347 User’s Manual C166S V1 SubSystem The External Bus Interface and bit field BTYP is loaded with the bus configuration selected via conf_rst_bustyp_i[1:0]. Field Bits Type Description MCTC [3:0] rw Memory Cycle Time Control (Number of memory cycle time waitstates) 0000: 15 waitstates .
Page 348 User’s Manual C166S V1 SubSystem The External Bus Interface Field Bits Type Description BSWCx BUSCON Switch Control Address windows are switched immediately A tristate waitstate is inserted if the next bus cycle accesses a different window than the one controlled by...
Page 349 User’s Manual C166S V1 SubSystem The External Bus Interface ADDRSEL3 Address Select Register 3 SFR (FE1C Reset value: 0000 RGSAD RGSZ ADDRSEL4 Address Select Register 4 SFR (FE1E Reset value: 0000 RGSAD RGSZ Field Bits Type Description RGSZ [0:3] Range Size Selection Defines the size of the address area controlled by the respective BUSCONx/ADDRSELx register pair.
Page 350 User’s Manual C166S V1 SubSystem The External Bus Interface Definition of Address Areas The four register pairs BUSCON4/ADDRSEL4-BUSCON1/ADDRSEL1 allow 4 address areas to be defined within the address space of the C166S. Within each of these address areas, external accesses can be controlled by one of the four different bus modes, independent of each other and of the bus mode specified in register BUSCON0.
Page 351 User’s Manual C166S V1 SubSystem The External Bus Interface Priority 1: The XADRSx registers are evaluated first. A match with one of these registers directs the access to the respective X-Peripheral using the corresponding XBCONx register and ignoring all other ADDRSELx registers. Priority of the XADRSx registers: XADR1 (priority I.1) , XADRS2 (I.2), XADRS3 (I.3), XADR4 (I.4) , XADRS5...
Page 352: Ebc Idle State
User’s Manual C166S V1 SubSystem The External Bus Interface Function Write Configuration Pins WR and BHE operate as WRL and WRH signals Pins WR and BHE operate as WR and BHE signals CSSEL Chip Select Line Selection (Number of active CS outputs) 3 CS lines: CS2...CS0...
Page 353: External Bus Arbitration
User’s Manual C166S V1 SubSystem The External Bus Interface Due to timing constraints, address and write data of an XBUS cycle are reflected on the external bus interface (see Table 8-7 below). The “address” mentioned above includes Port 4, BHE, and ALE (which also pulses for an XBUS cycle). The external CS signals are driven inactive (high) because the EBC switches to an internal XCS signal.
Page 354 User’s Manual C166S V1 SubSystem The External Bus Interface access to the external bus. All actions that just require internal resources such as instruction, data memory, or on-chip peripherals may be executed in parallel. When the C166S needs access to its external bus while it is occupied by another bus master, it demands it via the BREQ output.
Page 355 User’s Manual C166S V1 SubSystem The External Bus Interface C166S that has surrendered its bus interface to regain control of it in case it must access the shared external resources. This glue logic is required if the other bus master does not automatically remove its hold request after having used the shared resources.
Page 356 User’s Manual C166S V1 SubSystem The External Bus Interface Should the C166S require access to its external bus during hold mode, it activates its bus request output BREQ to notify the arbitration circuitry. BREQ is activated only during hold mode. It will be inactive during normal operation.
Page 357: The Xbus Interface
User’s Manual C166S V1 SubSystem The External Bus Interface • the C166S needs access to the shared resources and demands this by activating its BREQ output. The arbitration logic may then deactivate the other master’s HLDA and so free the external bus for the C166S, depending on the priority of the different masters.
Page 358 User’s Manual C166S V1 SubSystem The External Bus Interface the standard ADDRSEL registers. As the register pairs control integrated peripherals rather than externally connected ones, most of the registers are fixed by mask programming rather than being user-programmable. The XBUS provides byte-wide or word-wide X-Peripheral accesses. Because the on- chip connection can be very efficient, and for performance reasons, X-Peripherals are implemented only with a separate address bus, i.e., in demultiplexed bus mode.
Page 359: Xbus Access Control
User’s Manual C166S V1 SubSystem The External Bus Interface Field Bits Type Description PER4 XPeripheral Enable Control for XCS5 XPeripheral disabled XPeripheral enabled PER5 XPeripheral Enable Control for XCS6 XPeripheral disabled XPeripheral enabled PERx [15:6] XPeripheral Enable Control for XCSx, x=7..16...
Page 360 User’s Manual C166S V1 SubSystem The External Bus Interface The address range and address range start definition of XADRS5 and XADRS6 registers is identical to the address selection definition for external devices (see Address Window Definition). It is thus possible to use the whole address range also for internal memories or peripherals.
Page 361 User’s Manual C166S V1 SubSystem The External Bus Interface Field Bits Type Description MCTCx [3:0] Memory Cycle Time Control (number of wait states). See BUSCON BTYPx XBUS Type Definition 8-bit Demultiplexed Bus 16-bit Demultiplexed Bus BUSACTx XBUS Active Control XBUS (peripheral) disabled...
Page 362 User’s Manual C166S V1 SubSystem The External Bus Interface User’s Manual 8-40 V 1.6, 2001-08...
Page 363 User’s Manual C166S V1 SubSystem Watchdog Timer Watchdog Timer To allow recovery from software or hardware failure, the User’s Manual provides a Watchdog Timer . If the software fails to service this timer before an overflow occurs, a watchdog timer reset can be initiated and a watchdog timer overflow can be signaled by wdtint_n_o.
Page 364: Operation Of The Watchdog Timer
User’s Manual C166S V1 SubSystem Watchdog Timer • by 128 (WDTIN = ’1’, WDTPRE = ’0’), or • by 256 (WDTIN = ’1’, WDTPRE = ’1’). Operation of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a non-bitaddressable read-only register.
Page 365 User’s Manual C166S V1 SubSystem Watchdog Timer the high byte of the watchdog timer register WDT with the preset value from bitfield WDTREL which is the high byte of register WDTCON. After being serviced the watchdog timer continues counting up from the value (<WDTREL> * 2 Note: SRVWDT always triggers a timer reload independent of the execution of the EINIT and DISWDT instruction.
Page 366 User’s Manual C166S V1 SubSystem Watchdog Timer The period P between servicing the watchdog timer and the next overflow can therefore be determined by the following formula: (1 + <WDTPRE> + <WDTIN>*6) * (2 - <WDTREL>*2 Note: For safety reasons, the user is advised to rewrite WDTCON each time before the watchdog timer is serviced.
Page 367: Asynchronous/Synchronous Serial Interface (Asc)
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) Asynchronous/Synchronous Serial Interface (ASC) 10.1 Introduction This document describes the Asynchronous/Synchronous Serial Interface (ASC). The ASC supports a certain protocol to transfer data via a serial interconnection. It is also connected to a parallel bus of a microcontroller. The implementation is similar to the implementation in the C166 microcontrollers, however its parameters are changeable to work with parallel busses of different width and with different protocols.
Page 368 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) Figure 10-1 shows all funtional relevant interfaces associated with the ASC Kernel. Clock Control Address Port Module Decoder Control (Kernel) Interrupt TBIR Control Product Module Interface Interface Figure 10-1 ASC Interface Diagram Figure 10-2 shows all of the registers associated with the ASC Kernel.
Page 369 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) Port Input Select Register The PISEL register controls the receiver input selection of the ASC module. PISEL Port Input Select Register (Reset value: 0000 Field Bits Typ Description Receiver Input Select...
Page 370: Operational Overview
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) 10.2 Operational Overview Figure 10-3 shows a block diagram of the ASC with its operating modes (asynchronous and synchronous mode). $V\QFKURQRXV Prescaler / Baudrate 0RGH Divider Timer Serial Port Control Receive / Transmit...
Page 371: General Operation
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) 10.3 General Operation The ASC supports full-duplex asynchronous communication up to 3.75 MBaud and half-duplex synchronous communication up to 7.5 MBaud (@ 60 MHz module clock). In Synchronous Mode, data are transmitted or received synchronous to a shift clock that is generated by the microcontroller.
Page 372 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) The operating mode of the serial channel ASC is controlled by its control register CON. This register contains control bits for mode and error check selection, and status flags for error identification.
Page 373 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) Field Bits Typ Description Framing Check Enable (Asynchronous Mode only) Ignore framing errors Check framing errors Overrun Check Enable Ignore overrun errors Check overrun errors rwh Parity Error Flag Set by hardware on a parity error (PEN=1).
Page 374 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) Field Bits Typ Description [14] Loopback Mode Enabled Loopback Mode disabled. Standard transmit/receive Mode Loopback Mode enabled [15] Baudrate Generator Run Control Bit Baudrate generator disabled (ASC inactive) Baudrate generator enabled Note: BR_VALUE should only be written if R=0.
Page 375: Asynchronous Operation
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) 10.3.1 Asynchronous Operation Asynchronous Mode supports full-duplex communication in which both transmitter and receiver use the same data frame format and the same baudrate. Data is transmitted on line TXD and received on line RXD.
Page 376: Asynchronous Data Frames
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) 10.3.1.1 Asynchronous Data Frames 8-Bit Data Frames 8-bit data frames consist of either eight data bits D7...D0 (CON_M=’001 ’), or seven data bits D6...D0 plus an automatically generated parity bit (CON_M=’011 ’).
Page 377: Asynchronous Transmission
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) 11-/12-Bit UART Frame 9 Data Bits Start (1st) (2nd) Bit 9 Stop Stop &21B0 Bit 9 = Data Bit D8 &21B0 Bit 9 = Wake-up Bit &21B0 ...
Page 378: Asynchronous Reception
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) The transmit interrupt request line TIR will be activated before the last bit of a frame is transmitted, that is, before the first or the second stop bit is shifted out of the transmit shift register.
Page 379 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) receive circuit then waits for the next start bit (1-to-0 transition) at the receive data input line. RBUF Receive Buffer Register Reset value: 0000 RD_VALUE Field Bits Typ Description RD_VALUE [8:0]...
Page 380: Synchronous Operation
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) 10.3.2 Synchronous Operation Synchronous Mode supports half-duplex communication, basically for simple I/O expansion via shift registers. Data is transmitted and received via line RXD while line TXD outputs the shift clock.
Page 381: Synchronous Transmission
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) 10.3.2.1 Synchronous Transmission Synchronous transmission begins within four state times after data has been loaded into TBUF, provided that CON_R is set and CON_REN is cleared (half-duplex, no reception). Exception: in loopback mode (bit CON_LB set), CON_REN must be set for reception of the transmitted byte.
Page 382 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) Between two consecutive receive or transmit data bytes, one shift clock cycle (f ) delay is inserted. Shift Shift Shift Receive/Transmit Timing Latch Latch Shift Clock (TXD) Transmit Data Data Data...
Page 383: Baudrate Generation
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) 10.3.3 Baudrate Generation The serial channel ASC has its own dedicated 13-bit baudrate generator with reload capability, allowing baudrate generation independent of other timers. The baudrate generator is clocked with a clock (f...
Page 384 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) Field Bits Typ Description BR_VALUE [12:0] Baudrate Timer/Reload Value Reading returns the 13-bit contents of the baudrate timer; writing loads the baudrate timer/reload value. Note: BG should only be written if R=’0’.
Page 385 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) 13-Bit Reload Register Baud Fractional ÷16 Rate Divider Clock Sample 13-Bit Baudrate Timer ÷2 Clock ÷3 Selected Divider ÷ 2 ÷ 3 Fractional Divider Figure 10-9 ASC Baudrate Generator Circuitry in Asynchronous Modes...
Page 386 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) BG represents the contents of the reload register BG (BR_VALUE), taken as unsigned 13-bit integer. The maximum baudrate that can be achieved for the asynchronous modes when using the two fixed clock dividers and a module clock of 60 MHz is 1.875 MBaud.
Page 387: Baudrate In Synchronous Mode
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) Table 10-3 Asynchronous Baudrate Formulas using the Fractional Input Clock Divider Formula 1 ... 8191 1 ... 511 Baudrate = 16 x (BG+1) Baudrate = 16 x (BG+1) Table 10-4 Typical Asynchronous Baudrates using the Fractional Input Clock...
Page 388 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) 13-Bit Reload Register ÷2 Shift / 13-Bit Baudrate Timer ÷4 Sample Clock ÷3 Selected Divider ÷ 2 ÷ 3 Figure 10-10 ASC Baudrate Generator Circuitry in Synchronous Mode The baudrate for synchronous operation of serial channel ASC can be determined by the...
Page 389: Hardware Error Detection Capabilities
User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) 10.3.4 Hardware Error Detection Capabilities To improve the safety of serial data exchange, the serial channel ASC provides an error interrupt request flag to indicate the presence of an error, and three (selectable) error status flags in register CON to indicate which error has been detected during reception.
Page 390 User’s Manual C166S V1 SubSystem Asynchronous/Synchronous Serial Interface (ASC) For multiple back-to-back transfers, it is necessary to load the following piece of data until the time the last bit of the previous frame has been transmitted. In Asynchronous Mode, this leaves just one bit-time for the handler to respond to the transmitter interrupt request;...
Page 391: High-Speed Synchronous Serial Interface (Ssc)
User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) High-Speed Synchronous Serial Interface (SSC) 11.1 Introduction The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and half- duplex serial synchronous communication up to 30 MBaud (@ 60 MHz module clock).
Page 392 User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) Figure 11-1 shows all funtional relevant interfaces associated with the SSC Kernel. Clock Control Address Port Module Decoder Control (Kernel) EIRQ MS_CLK Interrupt RIRQ SS_CLK Control TIRQ Product Module Interface...
Page 393: General Operation
User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) 11.2 General Operation The SSC supports full-duplex and half-duplex synchronous communication up to 30 MBaud (@ 60 MHz module clock). The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from an external master (Slave Mode). Data width, shift direction, clock polarity, and phase are programmable.
Page 394 User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) Baudrate Clock SS_CLK Generator Control MS_CLK Shift Clock Receive Int. Request SSC Control Block Transmit Int. Request Register CON Error Int. Request Status Control TXD(Master) RXD(Slave) Control 16-Bit Shift Register...
Page 395: Operating Mode Selection
User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) 11.2.1 Operating Mode Selection The operating mode of the serial channel SSC is controlled by its control register CON. This register serves two purposes: – During programming (SSC disabled by CON.EN=0), it provides access to a set of control bits –...
Page 396 User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) Field Bits Type Description Loop Back Control Normal output Receive input is connected with transmit output (half-duplex mode) Transmit Error Enable Ignore transmit errors Check transmit errors Receive Error Enable...
Page 397 User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) Field Bits Type Description [3:0] Bit Count Field 0001 - 1111 Shift counter is updated with every shifted bit. Do not write to !!! Transmit Error Flag No error Transfer starts with the slave’s transmit buffer not...
Page 398 User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) The shift register of the SSC is connected to both the transmit lines and the receive lines via the pin control logic (see block diagram in Figure 11-3). Transmission and reception of serial data are synchronized and take place at the same time, i.e.
Page 399 User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) Field Bits Type Description RB_VALUE [15:0] Receive Data Register Value RB contains the received data value RB_VALUE. Unselected bits of RB will be not valid and should be ignored. Note: Only one SSC (etc.) can be master at a given time.
Page 400: Full-Duplex Operation
User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) CON. CON. Shift Clock MS_CLK/SS_CLK Pins MTSR/MRST Transmit Data First Last Latch Data Shift Data Figure 11-4 Serial Clock Phase and Polarity Options 11.2.2 Full-Duplex Operation The various devices are connected through three lines. The definition of these lines is always determined by the master: The line connected to the master’s data output line...
Page 401 User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) Master Device #1 Device #2 Slave Shift Register Shift Register Transmit MTSR MTSR Receive MRST MRST Clock Clock Clock Device #3 Slave Shift Register MTSR MRST Clock Figure 11-5 SSC Full-Duplex Configuration...
Page 402 User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave. After performing the necessary initialization of the SSC, the serial interfaces can be enabled.
Page 403: Half-Duplex Operation
User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) 11.2.3 Half-Duplex Operation In a Half-Duplex Mode, only one data line is necessary for both receiving and transmitting of data. The data exchange line is connected to both the MTSR and MRST pins of each device, the shift clock line is connected to the SCLK pin.
Page 404: Continuous Transfers
User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) 11.2.4 Continuous Transfers When the transmit interrupt request flag is set, it indicates that the transmit buffer TB is empty and ready to be loaded with the next transmit data. If TB has been reloaded by the time the current transmission is finished, the data is immediately transferred to the shift register and the next transmission will start without any additional delay.
Page 405: Baudrate Generation
User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) 11.2.5 Baudrate Generation The serial channel SSC has its own dedicated 16-bit baudrate generator with 16-bit reload capability, allowing baudrate generation independent of the timers. Figure 11-3 shows the baudrate generator.
Page 406 User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) BR = Baudrate = (<BR> + 1) Baudrate Field Bits Type Description BR_VALUE [15:0] Baudrate Timer/Reload Register Value Reading BR returns the 16-bit content of the baudrate timer. Writing BR loads the baudrate timer reload register with BR_VALUE.
Page 407: Error Detection Mechanisms
User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) 11.2.6 Error Detection Mechanisms The SSC is able to detect four different error conditions. Receive Error and Phase Error are detected in all modes; Transmit Error and Baudrate Error only apply to Slave Mode.
Page 408 User’s Manual C166S V1 SubSystem High-Speed Synchronous Serial Interface (SSC) A Phase Error (Master or Slave Mode) is detected when the incoming data at pin MRST (Master Mode) or MTSR (Slave Mode), sampled with the same frequency as the module clock, changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK.
Page 409: General Purpose Timer Unit
User’s Manual C166S V1 SubSystem General Purpose Timer Unit General Purpose Timer Unit 12.1 Introduction The General Purpose Timer Unit (GPT12E) provides very flexible multifunctional timer structures that may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. The GPT12E incorporates five 16-bit timers grouped into two timer blocks: Block 1 (GPT1) and Block 2 (GPT2).
Page 410 User’s Manual C166S V1 SubSystem General Purpose Timer Unit T6OFL Clock T3OUT T6OUT Control T2IN T3IN GPT12E T4IN Address T5IN Port Module T6IN Decoder CAPIN Control (Kernel) T2EUD T2IRQ T3EUD T3IRQ T4EUD Interrupt T4IRQ T5EUD T5EUD T5IRQ T6EUD Control T6IRQ...
Page 411: Functional Description Of Timer Block 1
User’s Manual C166S V1 SubSystem General Purpose Timer Unit 12.2 Functional Description of Timer Block 1 All three timers of Block 1 (T2, T3, T4) can run in four basic modes: Timer Mode, Gated Timer Mode, Counter Mode, and Incremental Interface Mode. All timers can count up or down.
Page 412 User’s Manual C166S V1 SubSystem General Purpose Timer Unit T2EUD Prescaler GPT1 Timer T2 T2IRQ Mode Control T2IN Reload Capture T3OTL T3IRQ Prescaler T3OUT T3IN Mode GPT1 Timer T3 T3OTL Control T3OE T3EUD T3OTL Capture Reload T4IN Mode Control GPT1 Timer T4...
Page 413: Core Timer T3
User’s Manual C166S V1 SubSystem General Purpose Timer Unit 12.2.1 Core Timer T3 The operation of core Timer T3 is controlled by its bitaddressable control register T3CON. Timer 3 (Reset value: 0000 Field Bits Typ Description [15:0] rwh Timer 3 Contains the current value of Timer 3.
Page 414 User’s Manual C166S V1 SubSystem General Purpose Timer Unit T3CON Timer 3 Control Register (Reset value: 0000 BPS1 RDIR Field Bits Typ Description [2:0] Timer 3 Input Parameter Selection Timer Mode: see Table 12-2 for encoding Gated Timer Mode: see...
Page 415 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description T3OE Overflow/Underflow Output Enable T3 overflow/underflow cannot be externally monitored via T3IN T3 overflow/underflow may be externally monitored via T3IN T3OTL [10] rwh Timer 3 Overflow Toggle Latch Toggles on each overflow/underflow of T3.
Page 416 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Count Direction Control The count direction of the core timer can be controlled either by software or by the external input line, T3EUD. These options are selected by bits T3UD and T3UDE in control register, T3CON.
Page 417 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Timer 3 in Timer Mode Timer Mode for core Timer T3 is selected by setting bitfield T3M in register T3CON to ‘000 ’. A block diagram of T3 in Timer Mode is shown in Figure 12-4.
Page 418 User’s Manual C166S V1 SubSystem General Purpose Timer Unit This formula also applies to T3 in Gated Timer Mode and to the auxiliary timers T2 and T4 in Timer Mode and Gated Timer Mode. BPS1 Prescaler Core Timer T3 T3IRQ...
Page 419 User’s Manual C166S V1 SubSystem General Purpose Timer Unit BPS1 Prescaler T3OUT T3OTL Core Timer T3 T3IN Down T3OE T3UD T3IRQ T3EUD T3UDE MCB02029_d Figure 12-5 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M = ‘010 ’, the timer is enabled when T3IN shows a low level.
Page 420 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Edge Select T3OUT T3IN Core Timer T3 T3OTL Down T3OE T3UD T3IRQ T3EUD T3UDE MCB02030_b Figure 12-6 Block Diagram of Core Timer T3 in Counter Mode Table 12-4 Core Timer T3 (Counter Mode) Input Edge Selection...
Page 421 User’s Manual C166S V1 SubSystem General Purpose Timer Unit T3OE T3OUT T3IN Edge Timer T3 T3OTL Select Down T3IRQ Edge RDIR T3IRQ T3UD Change T3IRQ Detection CHDIR Phase Detect T3EUD MCB03998_b T3UDE Figure 12-7 Block Diagram of Core Timer T3 in Incremental Interface Mode...
Page 422 User’s Manual C166S V1 SubSystem General Purpose Timer Unit The incremental encoder can be connected directly to the microcontroller without external interface logic. In a standard system, however, comparators will be employed to convert the encoder’s differential outputs (such as A, A) to digital signals (such as A Figure 12-8).
Page 423 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Forward Jitter Backward Jitter Forward T3IN T3EUD Contents of T3 Note: This example shows the timer behavior assuming that T3 counts upon any transition on any input, i.e. T3I = ’011 ’.
Page 424: Auxiliary Timers T2 And T4
User’s Manual C166S V1 SubSystem General Purpose Timer Unit 12.2.2 Auxiliary Timers T2 and T4 Timer 2 (Reset value: 0000 Timer 4 (Reset value: 0000 T2CON Timer 2 Control Register (Reset value: 0000 RDIR T4CON Timer 4 Control Register (Reset value: 0000...
Page 425 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description [2:0] Timer x Input Parameter Selection Timer Mode: see Table 12-7 for encoding Gated Timer Mode: see Table 12-7 for encoding Counter Mode: see Table 12-8 for encoding...
Page 426 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description TxIRDIS [12] Timer x Interrupt Disable Interrupt generation for TxCHDIR and TxEDGE interrupts in Incremental Interface Mode is enabled Interrupt generation for TxCHDIR and TxEDGE interrupts in Incremental Interface...
Page 427 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Timers T2 and T4 in Timer Mode or Gated Timer Mode When the auxiliary Timers T2 and T4 are programmed to Timer Mode or Gated Timer Mode, their operation is the same as described for the core Timer T3. The descriptions, figures, and tables apply accordingly with two exceptions: •...
Page 428 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Timers T2 and T4 in Counter Mode In Counter Mode, Timers T2 and T4 can be clocked either by a transition at the respective external input line TxIN, or by a transition of T3OTL.
Page 429: Timer Concatenation
User’s Manual C166S V1 SubSystem General Purpose Timer Unit For counter operation, an external pin associated with line TxIN must be configured as input. The maximum input frequency allowed in Counter Mode is f /8 (BPS1 = ’01’). To ensure that a transition of the count input signal applied to TxIN is correctly recognized, its level should be held for at least 4 f cycles (BPS1 = ’01’) before it changes.
Page 430 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Auxiliary Timer in Reload Mode Reload Mode for the auxiliary timers T2 and T4 is selected by setting bitfield TxM in the respective register TxCON to ‘100 ’. In Reload Mode, core Timer T3 is reloaded with the contents of an auxiliary timer register, triggered by one of two different signals.
Page 431 User’s Manual C166S V1 SubSystem General Purpose Timer Unit The Reload Mode triggered by T3OTL can be used in a number of different configurations. Depending on the selected active transition, the following functions can be performed: • If both a positive and a negative transition of T3OTL are selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows.
Page 432 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Auxiliary Timer T2 T2IRQ BPS1 T3OUT Prescaler Core Timer T3 T3OTL Up/Down T3OE T3IRQ T4IRQ Auxiliary Timer T4 MCB02037_b Figure 12-14 GPT1 Timer Reload Configuration for PWM Generation Note: Line ’*)’ is affected by over/underflow of T3 only, NOT by software modifications...
Page 433 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Edge Select Auxiliary Timer Tx TxIN TxIRQ Core Timer T3 T3IRQ BPS1 T3OUT Prescaler Up/Down T3OTL x = 2,4 MCB02038_b T3OE Figure 12-15 Auxiliary Timer of Timer Block 1 in Capture Mode...
Page 434: Functional Description Of Timer Block 2
User’s Manual C166S V1 SubSystem General Purpose Timer Unit 12.3 Functional Description of Timer Block 2 Timer Block 2 includes the two Timers T5 (referred to as the auxiliary timer) and T6 (referred to as the core timer), and the 16-bit capture/reload register CAPREL. Each timer of Block 2 is controlled by a separate control register, TxCON.
Page 435 User’s Manual C166S V1 SubSystem General Purpose Timer Unit T5EUD Prescaler Mode Control T5IN GPT2 Timer T5 T5IRQ Clear Capture CAPIN CRIRQ T3IN/ GPT2 CAPREL T3EUD T6IRQ Clear T3OUT GPT2 Timer T6 T6OTL T6IN T3OE Prescaler Mode T6OFL Control T6EUD...
Page 436: Core Timer T6
User’s Manual C166S V1 SubSystem General Purpose Timer Unit 12.3.1 Core Timer T6 The operation of the core Timer T6 is controlled by its bitaddressable control register T6CON. Timer 6 (Reset value: 0000 T6CON Timer 6 Control Register (Reset value: 0000...
Page 437 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description T6UD Timer 6 Up / Down Control (when T6UDE = ’0’) Counts Up Counts Down T6UDE Timer 6 External Up/Down Enable Counting direction is internally controlled by...
Page 438 User’s Manual C166S V1 SubSystem General Purpose Timer Unit In Gated Timer Mode, the timer will run only if T6R is set and the gate is active (high or low, as programmed). Note: When bit T5RC is set, bit T6R will also control (start and stop) auxiliary Timer T5.
Page 439 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Timer 6 in Timer Mode Timer Mode for core Timer T6 is selected by setting bitfield T6M in register T6CON to ‘000 ’. In this mode, T6 is clocked with the module clock divided by a programmable prescaler, as selected by bitfield T6I.
Page 440 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Table 12-11 Timer 6 Input Parameter Selection: Timer and Gated Timer Modes Prescaler for f Prescaler for f Prescaler for f Prescaler for f (BPS2 = 00) (BPS2 = 01) (BPS2 = 10)
Page 441 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Timer 6 in Counter Mode Counter Mode for core Timer T6 is selected by setting bitfield T6M in register T6CON to ‘001 ’. In Counter Mode, Timer T6 is clocked by a transition at the external input line T6IN.
Page 442: Auxiliary Timer T5
User’s Manual C166S V1 SubSystem General Purpose Timer Unit The maximum input frequency allowed in Counter Mode is f /4 (BPS2 = ’01’). To ensure that a transition of the count input signal applied to T6IN is correctly recognized, its level should be held high or low for at least 2 f cycles (BPS2 = ’01’) before it changes.
Page 443 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description [2:0] Timer 5 Input Parameter Selection Timer Mode: see Table 12-13 for encoding Gated Timer Mode: see Table 12-13 for encoding Counter Mode: see Table 12-14 for encoding...
Page 444 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description [13:12] rw Register CAPREL Capture Trigger Selection (depending on bit CT3) Capture disabled Positive transition (rising edge) on CAPIN or any transition on T3IN Negative transition (falling edge) on CAPIN or...
Page 445 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Table 12-13 Timer 5 Input Parameter Selection: Timer and Gated Timer Modes Prescaler for f Prescaler for f Prescaler for f Prescaler for f (BPS2 = 00) (BPS2 = 01) (BPS2 = 10)
Page 446: Timer Concatenation
User’s Manual C166S V1 SubSystem General Purpose Timer Unit The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at either the input line T5IN or at the toggle latch T6OTL.
Page 447 User’s Manual C166S V1 SubSystem General Purpose Timer Unit BPS2 T6OUT Prescaler Core Timer T6 T6OTL T6OE Up/Down T6IRQ Edge Select T5IRQ Auxiliary Timer T5 T5IR T5IN MCB02034_e Up/Down Figure 12-22 Concatenation of Core Timer T6 and Auxiliary Timer T5 Note: Line ’*)’...
Page 448 User’s Manual C166S V1 SubSystem General Purpose Timer Unit or input T3EUD or both inputs T3IN and T3EUD. The active edge is controlled by bitfield CI in register T5CON. The maximum input frequency for the capture trigger signal at CAPIN is f /2 (BPS2 = ’01’).
Page 449 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Timer Block 2 Capture/Reload Register CAPREL in Reload Mode This 16-bit register can be used as a reload register for core Timer T6. This mode is selected by setting bit T6SR in register T6CON. The event causing a reload in this mode is an overflow or underflow of core Timer T6.
Page 450 User’s Manual C166S V1 SubSystem General Purpose Timer Unit Timer Block 2 Capture/Reload Register CAPREL in Capture-And-Reload Mode Because the reload and capture functions of register CAPREL can be enabled individually by bits T5SC and T6SR, the two functions can be enabled simultaneously by setting both bits.
Page 451 User’s Manual C166S V1 SubSystem General Purpose Timer Unit register CAPREL, and Timer T5 is cleared (T5CLR cleared). Thus, register CAPREL always contains the correct time between two events, measured in Timer T5 increments. Timer T6, which runs in Timer Mode counting down with a frequency of f /4, for example, uses the value in register CAPREL to perform a reload on underflow.
Page 452 User’s Manual C166S V1 SubSystem General Purpose Timer Unit User’s Manual 12-44 V 1.6, 2001-08...
Page 453: Instruction Index
User’s Manual C166S V1 SubSystem Instruction Index Instruction Index This section lists alphabetically all C166S instructions together with references to respective pages holding the detailed descriptions. This helps to quickly find the explanation of any specific core instruction. ADD ..6-2 DIVL .
Page 454 User’s Manual C166S V1 SubSystem Instruction Index User’s Manual 13-2 V 1.6, 2001-08...
Page 455: Keyword Index
User’s Manual C166S V1 SubSystem Keyword Index Keyword Index This section lists a number of keywords which refer to specific details of the C166S V1 SubS R1 in terms of its architecture, its functional units or functions. This helps to quickly find the answer to specific questions about the C166S V1 SubS R1.
Page 456 User’s Manual C166S V1 SubSystem Keyword Index Read/Write 8-18 Internal Demultiplexed Bus Development Support Interrrupt Control Register 3-21, 3-44 Direction Interrupt count 12-8, 12-30 System 2-6, 3-19 DP0L, DP0H Interrupt Sources 4-43, 4-48 DP1L, DP1H IP Register 3-15 DP4 7-10,...
Page 457 User’s Manual C166S V1 SubSystem Keyword Index PECSNx Register 3-35 S0RBUF 10-13, 10-15 Peripheral S0TBUF 10-11, 10-15 Summary 2-12 Peripheral Event Controller 3-32 Segment Pipeline Address 8-12 Effects 3-80 boundaries PLEV 3-36 Serial Interface Power Saving Control 2-13 Asynchronous 10-9...
Page 458 User’s Manual C166S V1 SubSystem Keyword Index Timer 6 Counter Mode 12-33 Timer 6 Gated Mode 12-32 12-16 Timer 6 Timer Mode 12-31 T2CON 12-16 Timer Block 1 12-3 T3CON 12-6 Timer Block 2 12-26 12-16 Timer T3 12-5 T4CON...
Page 460 Infineon goes for Business Excellence “Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.”...

Infineon C166S V1 SubSystem User Manual

1 Introduction

Watchdog Timer

2 System Overview

3 Central Processing Unit

4 Memory Organization

5 Instruction Set

Detailed Instruction Set

7 Parallel Ports

The External Bus Interface

Asynchronous/Synchronous Serial Interface (ASC)

High-Speed Synchronous Serial Interface (SSC)

12 General Purpose Timer Unit

Instruction Index

Keyword Index

Quick Links

Related Manuals for Infineon C166S V1 SubSystem

Summary of Contents for Infineon C166S V1 SubSystem

Table of Contents