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Low-power system design with AIROC™ Wi-Fi & Bluetooth® combo
chip and PSoC™ 6 MCU
PSoC™ 6 MCU power optimization techniques
5
PSoC™ 6 MCU power optimization techniques
5.1
Core voltage and operating frequency
PSoC™ 6 MCU supports two core regulators – LDO or Buck – either of which can be used to power the CPU core.
In addition, the system supports two active power modes – System LP and System ULP. In the System LP power
mode, the CPU frequency can reach up to 150 MHz, whereas in the System ULP mode, the CPU frequency is
limited to 50 MHz. The power consumed by the CPU is much lower in System ULP mode.
By default, the LDO powers the core and it is in System LP mode. The LDO regulator consumes a higher power
than the buck regulator in active mode (>50%) for the same CPU clock frequency irrespective of the LP or ULP
mode. However, in LP mode, the leakage in Deep Sleep is lower (~20%) using the LDO regulator as compared to
the buck regulator. Unless the application spends < 0.01% time in active mode (1 ms out of 10 s), it is
recommended to use the buck regulator as the core regulator because the added leakage in Deep Sleep using
the buck regulator is outweighed by the power saving in active mode. When using ULP mode for active power
mode, it is always recommended to use the buck regulator because the leakage in ULP mode is lower than the
LDO in System ULP mode.
Table 6
Core regulator and active power mode selection
Application use case
(CPU Clock > 50 MHz OR Peri Clock > 25 MHz) AND
CPU active/sleep time < 0.01 %.
0.01 % = 1 ms out of 10 s.
(CPU Clock > 50 MHz OR Peri Clock > 25 MHz) AND
CPU active/sleep time > 0.01 %.
0.01 % = 1 ms out of 10 s.
(CPU Clock < 50 MHz AND Peri Clock < 25 MHz)
See
AN219528
for details on the power modes and
parameters.
5.2
Reducing the leakage in Deep Sleep
PSoC™ 6 MCU supports selective retention of SRAM in sizes of 32 KB when the device enters Deep Sleep. The
smaller the amount of SRAM retained in Deep Sleep, the lower the Deep Sleep power consumption will be. If
the application knows the amount of SRAM it plans to use, the unused SRAM blocks can be disabled to improve
the Deep Sleep power consumption. However, some guidelines must be kept in mind while disabling the SRAM
blocks:
A few platforms, allocate the unused SRAM to the heap. As a result, the amount of SRAM consumed by the
1.
heap (or dynamically allocated objects in the code) should be considered and added to the budget.
2. System calls supported in PSoC™ 6 MCU use 2 KB of SRAM available at the end of the SRAM region present in
the device. As a result, if the application uses/requires any system calls, such as flash write/erase, it must
not disable the last block of the SRAM (block 8 in PSoC™ 6 MCU devices with 288 KB RAM). However, the
block can still be turned off before entering Deep Sleep (because system calls are executed in active mode
only).
All projects should reserve 8 KB (0x2000) of SRAM at the start of the SRAM region for the CM0+ core; this
3.
should be accounted into the overall SRAM consumption of the application.
Application note
Core regulator
LDO
Buck
Buck
PSoC™ 6 MCU datasheet
26
System active power mode
LP
LP
ULP
for details on the power
002-27910 Rev. *C
2023-05-29
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