Infineon C513AO User Manual
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Infineon C513AO User Manual

Infineon C513AO User Manual

8-bit cmos microcontroller
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Microcomputer Components
8-bit CMOS Microcontroller
C513AO
User's Manual 05.99
DS 1

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Summary of Contents for Infineon C513AO

  • Page 1 Microcomputer Components 8-bit CMOS Microcontroller C513AO User’s Manual 05.99 DS 1...
  • Page 2 Information For further information on technology, deliv- ery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technolo- gies Representatives worldwide (see ad- dress list). Warnings Due to technical requirements components may contain dangerous substances.
  • Page 3 C513AO Revision History: 05.99 Previous Releases: Page Subjects We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.

  • Page 4: Table Of Contents

    General Information C513AO Contents Page Introduction ............1-1 Pin Configurations .
  • Page 5 General Information C513AO Contents Page 6.2.1.4 Mode 2 ............6-21 6.2.1.5...
  • Page 6 General Information C513AO Contents Page 9.3.2 Exit from Power-down Mode ......... . . 9-7 OTP Memory Operation .

  • Page 7: Introduction

    The C513AO-L is the version without program memory. The term C513AO refers to all versions within the documentation unless otherwise noted. Figure 1-1 shows the basic functional units of the C513AO. Figure 1-2 shows the simplified logic symbol of the C513AO device.
  • Page 8 Fully pin-compatible with C501, C504, C505C, C505CA and C511/C513-devices. : 0 to 70 °C • Temperature ranges: SAB-C513AO : – 40 to 85 °C SAF-C513AO 1)“Enhanced Hooks Technology” is a trademark and patent of MetaLink Corporation licensed to Infineon Technologies. User’s Manual 05.99...
  • Page 9 Introduction C513AO Port 0 8-Bit Digital I/O XTAL1 XTAL2 Port 1 8-Bit Digital I/O RESET C513AO Port 2 8-Bit Digital I/O PSEN Port 3 8-Bit Digital I/O MCL04007 Figure 1-2 Logic Symbol User’s Manual 05.99...

  • Page 10: Pin Configurations

    Introduction C513AO Pin Configurations This section describes the pin configurations of the C513AO device in various packages. P1.0/T2 P1.1/T2EX P0.0/AD0 P1.2/SCLK P0.1/AD1 P1.3/SRI P0.2/AD2 P1.4/STO P0.3/AD3 P1.5/SLS P0.4/AD4 P1.6 P0.5/AD5 P1.7 P0.6/AD6 P0.7/AD7 RESET P3.0/RxD C513AO P3.1/TxD P3.2/INT0 PSEN P3.3/INT1 P2.7/A15...
  • Page 11 Introduction C513AO 28 27 26 25 24 23 22 21 20 19 18 P2.5/A13 P3.5/T1 P2.6/A14 P3.4/T0 P2.7/A15 P3.3/INT1 PSEN P3.2/INT0 P3.1/TxD C513AO N.C. N.C. P3.0/RxD P0.7/AD7 RESET P0.6/AD6 P1.7 P0.5/AD5 P1.6 P0.4/AD4 P1.5/SLS 40 41 42 43 44 1 2 3 4 5 6...
  • Page 12 Introduction C513AO 32 31 30 29 28 27 26 25 24 23 P0.3/AD3 P2.4/A12 P0.2/AD2 P2.3/A11 P0.1/AD1 P2.2/A10 P0.0/AD0 P2.1/A9 P2.0/A8 C513AO P1.0/T2 P1.1/T2EX XTAL1 P1.2/SCLK XTAL2 P1.3/SRI P3.7/RD P1.4/STO P3.6/WR 9 10 11 MCP04010 Figure 1-5 P-MQFP-44 Package Pin Configuration (top view) User’s Manual...

  • Page 13: Pin Definitions And Functions

    Introduction C513AO Pin Definitions and Functions This section describes all external signals to the C513AO and their functions. Table 1-1 Pin Definitions and Functions Symbol Pin Number Function P1.7- 3-1, I/O Port 1 P1.0 44-40 Port 1 is an 8-bit quasi-bidirectional port with internal pull- up arrangement.
  • Page 14 Introduction C513AO Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number Function P3.0- 10-17 I/O Port 3 P3.7 13-19 7-13 Port 3 is an 8-bit quasi-bidirectional port with internal pull- up arrangement. Port 3 pins that have “1”s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs.
  • Page 15 Introduction C513AO Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number Function RESET RESET A high level on this pin for the duration of two machine cycles while the oscillator is running resets the device. An internal diffused resistor to...
  • Page 16 PC is less than 4000 When held at low level, the C5 13AO fetches all instructions from external program memory. This pin should not be driven during reset operation. Note: For the C513AO-L this pin must be tied low. P0.0- 32-39 43-36 37-30 I/O Port 0 P0.7...
  • Page 17 Introduction C513AO Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number Function – Ground (0 V) – – Ground (0 V), Optional This pin may be left unconnected. It is, however, recommended to connect this pin to for optimized EMC performance –...

  • Page 18: Fundamental Structure

    The C513AO family of microcontrollers is based on the C501 architecture. Therefore, they are also fully compatible with the industry-standard 8051 microcontrollers. The synchronous serial channel and the external memory (XRAM) are important features of the C513AO not found in the C501. Figure 2-1 illustrates the major blocks of the C513AO device.

  • Page 19: Central Processing Unit (Cpu)

    C513AO Central Processing Unit (CPU) The C513AO is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions.
  • Page 20 Fundamental Structure C513AO Special Function Register PSW (Address D0 Reset Value: 00 Bit No. MSB Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag 0 Register bank Select control bits These bits are used to select one of the four register banks.

  • Page 21: Cpu Timing

    Figure 2-2 (a) and (b) show the timing for a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction, respectively. Most C513AO instructions are executed in one cycle. Multiply (MUL) and divide (DIV) are the only instructions that take more than two cycles to complete; they take four cycles. Normally, two code bytes are fetched from the program memory during every machine cycle.
  • Page 22 Fundamental Structure C513AO Figure 2-2 Fetch Execute Sequence User’s Manual 05.99...

  • Page 23: Memory Organization

    Memory Organization The C513AO CPU manipulates operands in the following four address spaces: • Up to 64 Kbytes of program memory (up to 16 KB on-chip program memory for the C513AO-2E/ • Up to 64 Kbytes of external data memory •...

  • Page 24: Program Memory, "Code Space

    The C513AO-2E/2R device has 16 Kbytes of program memory and can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C513AO-2E/2R executes program code from the on-chip program memory unless the program counter address exceeds 3FFF .

  • Page 25: Xram Operation

    XRAM Operation The XRAM in the C513AO is a memory area that is logically located at the upper end of the external data memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory, the same instruction types must be used for accessing the XRAM.

  • Page 26: Accesses To Xram Using The Registers R0/R1 (8-Bit Addressing Mode)

    C513AO 3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode) The C513AO architecture provides instructions for accesses to external data memory and XRAM which use an 8-bit address (indirect addressing with Registers R0 or R1). These instructions are: –...

  • Page 27: Special Function Registers

    CPU and the other on-chip peripherals. The SFRs of the C513AO are listed in Table 3-1 and Table 3-2. In Table 3-1, they are organized in groups which refer to the functional blocks of the C513AO. Table 3-2 illustrates the contents of the SFRs in numeric order of their addresses.
  • Page 28 4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) This SFR is read-only. 6) C513AO-L/2R: 13H C513AO-2E: 83H 7) This SFR varies with the step of the microcontroller: for example, 01 for the first step 8) This register is only used for test purposes and must not be written during normal operation.
  • Page 29 4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) This SFR is read-only. 6) C513AO-L/2R: 13H C513AO-2E: 83H 7) This SFR varies with the step of the microcontroller: for example, 01 for the first step 8) This register is only used for test purposes and must not be written during normal operation.
  • Page 30 Memory Organization C513AO Table 3-2 Contents of the SFRs, SFRs in Numeric Order of Their Addresses Addr Register Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 after Reset WDTREL 00 PSEL...
  • Page 31 5) The content of this SFR varies with the actual step of the C513A0: for example, 01 for the first step) 6) This register is only used for test purposes and must not be written during normal operation. Unpredictable results may occur upon a write operation. 7) C513AO-L/2R: 13 C513AO-2E: 83 User’s Manual 05.99...

  • Page 32: External Bus Interface

    8051 architecture with one exception: if the C513AO is used in systems with no external memory, the generation of the ALE signal can be suppressed. By resetting bit EALE in the SFR SYSCON register, the ALE signal will not be generated externally.
  • Page 33 External Bus Interface C513AO One Machine Cycle One Machine Cycle PSEN without MOVX INST INST INST INST INST PCL OUT PCL OUT PCL OUT PCL OUT valid valid valid valid One Machine Cycle One Machine Cycle PSEN with MOVX DPH OUT OR...

  • Page 34: Timing

    Port 2 is dedicated at all times to output of the high-order address byte. This means that Port 0 and Port 2 of the C513AO-L can never be used as general-purpose I/O. This also applies to the C513AO-2R or C513AO-2E if they are operated with only an external program memory.

  • Page 35: Address Latch Enable (Ale)

    This can be useful if the external memory is accessed only rarely. The C513AO allows the ALE output signal to be switched off. If the internal program memory is used by setting EA = 1 and ALE is switched off by setting EALE = 0, ALE will only go active during external data memory accesses (MOVX instructions) and code memory accesses with an address greater than 3FFF H (external code memory fetches).

  • Page 36: Enhanced Hooks Emulation Concept

    Hooks Emulation Concept to control the operation of the device during emulation and to transfer information about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1)“Enhanced Hooks Technology” is a trademark and patent of MetaLink Corporation licensed to Infineon Technologies. User’s Manual...

  • Page 37: Rom/Otp Protection

    4.5.1 Unprotected ROM Mode If the ROM is unprotected, ROM Verification Mode 1, shown in Figure 4-3, is used to read out the content of the ROM. (See also the AC Specifications in the Data Sheet; not valid for C513AO-2E). P1.0-P1.7 Address P2.0-P2.5...

  • Page 38: Protected Rom/Otp Mode

    C513AO 4.5.2 Protected ROM/OTP Mode For the C513AO-2R ROM protected by mask, and for the C513AO-2E OTP in Protection Level 1, ROM/OTP Verification Mode 2, shown in Figure 4-4, is used to verify the content of the ROM/OTP. The detailed timing characteristics of the ROM/OTP verification mode are shown in the data sheet.
  • Page 39 16 verify operations is output at P3.5. P3.5 is always set or cleared after each 16 byte block of the verify sequence. In ROM/OTP Verification Mode 2, the C513AO must be provided with a system clock at the XTAL pins.

  • Page 40: Reset And System Clock Operation

    Power-down Mode is to be terminated. In addition to the hardware reset, which is applied externally to the C513AO, there are two internal reset sources: the Watchdog Timer and the Oscillator Watchdog. This chapter deals with the external hardware reset only.
  • Page 41 I/O port lines (Ports 1 to 3) output “1”s. The contents of the internal RAM and XRAM of the C513AO are not affected by a reset. After power-up, the contents are undefined, while it remains unchanged during a reset if the power supply is not turned off.

  • Page 42: Fast Internal Reset After Power-On

    C513AO Fast Internal Reset after Power-On The C513AO uses the Oscillator Watchdog unit for a fast internal reset procedure after power-on. Figure 5-2 shows the power-on sequence under control of the Oscillator Watchdog. Normally, devices in the 8051 microcontroller family do not enter their default reset state before the on-chip oscillator starts.
  • Page 43 Reset / System Clock C513AO Figure 5-2 Power-On Reset Timing of the C513AO User’s Manual 05.99...

  • Page 44: Hardware Reset Timing

    XTAL1 and XTAL2 pins). The RESET signal must be active for at least two machine cycles; after this interval, the C513AO remains in its reset state as long as the signal is active. When the signal goes inactive, this transition is recognized in the subsequent S5P2 of the machine cycle.

  • Page 45: Oscillator And Clock Circuit

    Reset / System Clock C513AO Oscillator and Clock Circuit XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter which can be configured with off-chip components as a pierce oscillator. The oscillator, in any case, drives the internal clock generator.
  • Page 46 Figure 5-5 On-Chip Oscillator Circuitry To drive the C513AO with an external clock source, the external clock signal must be applied to XTAL1, as shown in Figure 5-6. XTAL2 must be left unconnected. A pull-up resistor is suggested to increase the noise margin, but is optional if of the driving gate corresponds to the specification of XTAL1.

  • Page 47: On-Chip Peripheral Components

    On-Chip Peripheral Components Parallel I/O The C513AO has four 8-bit I/O ports. Port 0 is an open-drain bidirectional I/O port, while Ports 1, 2, and 3 are quasi-bidirectional I/O ports with internal pull-up resistors. Thus, when configured as inputs, Ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input.
  • Page 48 On-Chip Peripheral Components C513AO Ports 1, 2, and 3 output drivers have internal pull-up FETs (see Figure 6-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit must contain a 1 (that means for Figure 6-2: Q = 0), which turns off the output driver FET n1.
  • Page 49 On-Chip Peripheral Components C513AO Delay = 2 Osc. Periodes < Port Input Data (read pin) MCS01824 Figure 6-3 Output Driver Circuit of Ports 1, 2 and 3 (except P1.2, P1.3, P1.4 and P1.5) One n-channel pull-down FET and three pull-up FETs are used in the example shown in Figure 6-3.
  • Page 50 On-Chip Peripheral Components C513AO The activating and deactivating of the four different transistors results in one of these four states: • Input Low state (IL), p2 active only • Input High state (IH) = Steady Output High state (SOH), p2 and p3 active •...
  • Page 51 On-Chip Peripheral Components C513AO Delay = 2 Osc. Periods Enable Push-pull & < < < Port & < Tristate Input Data (Read Pin) MCS02432 Figure 6-4 Driver Circuit of Port 1 Pins P1.2 and P1.4 (when used for SLCK and STO) Pin Control for SCLK When the SSC is disabled, both Enable Push-pull and Tristate will be inactive;...
  • Page 52 On-Chip Peripheral Components C513AO Delay = 2 Osc. Periods < < Port & < Tristate Input Data (Read Pin) MCS02433 Figure 6-5 Driver Circuit of Port 1 Pins P1.3 and P1.5 (when used for SRI and SLS) When enabling the SSC, inputs used for the SSC will be switched into high-impedance mode.
  • Page 53 On-Chip Peripheral Components C513AO Port 0, in contrast to Ports 1, 2, and 3, is considered as “true” bidirectional, because the Port 0 pins float when configured as inputs. Thus, this port differs in not having internal pull-ups. The pullup FET in the P0 output driver (see Figure 6-6) is used only when the port is emitting “1”s during the...

  • Page 54: Port 0 And Port 2 Used As Address/Data Bus

    On-Chip Peripheral Components C513AO 6.1.2 Port 0 and Port 2 used as Address/Data Bus As shown in Figure 6-6 and in Figure 6-7 respectively, the output drivers of Port 0 and Port 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally.

  • Page 55: Alternate Functions

    On-Chip Peripheral Components C513AO 6.1.3 Alternate Functions The pins of Ports 1 and 3 are multifunctional. They are port pins and also serve to implement alternate functions (special inputs/outputs for on-chip peripherals) as listed in Table 6-1. Figure 6-7 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, the gate between the latch and the driver circuit must be open.
  • Page 56 On-Chip Peripheral Components C513AO Read Latch Int. Bus Latch Write to Latch Port Read Alternate Input MCS02435 Function Figure 6-9 Port Pins P1.2, P1.3 and P1.5 (when used as SSC inputs) Alternate Output Read Function Latch Port & Int. Bus...
  • Page 57 On-Chip Peripheral Components C513AO Ports 1 and 3 provide several alternate functions as listed in Table 6-1. Table 6-1 Alternate Functions of Ports 1 and 3 Port Symbol Function P1.0 Input to Counter 2 P1.1 T2EX Capture-reload trigger of Timer 2/up-down count P1.2...

  • Page 58: Port Timing

    On-Chip Peripheral Components C513AO 6.1.4 Port Timing When executing an instruction which changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2, the output buffer holds the value it noticed during the previous phase 1).

  • Page 59: Port Loading And Interfacing

    The output buffers of Ports 2 and 3 can drive TTL inputs directly. Refer to the DC characteristics in the Data Sheet of the C513AO for the maximum port load which still guarantees correct logic output levels. The corresponding parameters are The output buffers of Port 0 can also drive TTL inputs directly.

  • Page 60: Read-Modify-Write Feature Of Ports 2 And 3

    On-Chip Peripheral Components C513AO 6.1.6 Read-Modify-Write Feature of Ports 2 and 3 Some port-reading instructions read the latch and others read the pin. The instructions reading the latch (rather than the pin) read a value, possibly change it, and then rewrite it to the latch. These are called “read-modify-write”...

  • Page 61: Timers/Counters

    6.2.1 Timer/Counter 0 and 1 Timer/Counter 0 and Timer/Counter 1 of the C513AO are fully compatible with Timer/Counter 0 and Timer/Counter 1 of the C501 and can be used in the same four operating modes:...

  • Page 62: Timer/Counter 0 And 1 Registers

    On-Chip Peripheral Components C513AO 6.2.1.1 Timer/Counter 0 and 1 Registers Six special function registers control Timer/Counter 0 and 1 operation: • TL0/TH0 and TL1/TH1 are counter registers with low and high bytes. • TCON and TMOD are control and mode select registers.
  • Page 63 On-Chip Peripheral Components C513AO Special Function Register TCON (Address 88 H ) Reset Value: 00 H Bit No. 8F H 8E H 8D H 8C H 8B H 8A H 89 H 88 H 88 H TCON The shaded bits are not used in controlling Timer/Counter 0 and 1.
  • Page 64 On-Chip Peripheral Components C513AO Special Function Register TMOD (Address 89 H ) Reset Value: 00 H Bit No. 89 H GATE GATE TMOD Timer 1 Control Timer 0 Control Function GATE Gating control When set, Timer/Counter “x” is enabled only while “INT x” pin is high and “TRx”...

  • Page 65: Mode 0

    On-Chip Peripheral Components C513AO 6.2.1.2 Mode 0 Putting either Timer/Counter 0 or Timer/Counter 1 into Mode 0 configures it as an 8-bit timer/ counter with a divide-by-32 prescaler. Figure 6-12 shows Mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all “1”s to all “0”s, it sets the Timer overflow Flag, TF0.
  • Page 66 On-Chip Peripheral Components C513AO 6.2.1.3 Mode 1 Mode 1 is the same as Mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in Figure 6-13. ÷ 12 C/T = 0 Interrupt (8 Bits)
  • Page 67 On-Chip Peripheral Components C513AO 6.2.1.4 Mode 2 Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 6-14. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software.
  • Page 68 On-Chip Peripheral Components C513AO 6.2.1.5 Mode 3 Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters.

  • Page 69: Timer/Counter

    On-Chip Peripheral Components C513AO 6.2.2 Timer/Counter 2 Timer 2 is a 16-bit timer/counter and has three operating modes: • 16-bit auto-reload mode (up or down counting) • 16-bit capture mode • Baudrate generator (see Section 6.3.3 “Baudrates”) The modes are selected by bits in the SFR T2CON as shown in Table 6-3:...

  • Page 70: Timer/Counter 2 Registers

    On-Chip Peripheral Components C513AO 6.2.2.1 Timer/Counter 2 Registers Six special function registers control Timer/Counter 0 and 1 operation: • TL2/TH2 and RC2L/RC2H are counter and reload/capture registers with low and high bytes. • T2CON and T2MOD are control and mode select registers.
  • Page 71 On-Chip Peripheral Components C513AO Special Function Register T2CON (Address C8 H ) Reset Value: 00 H Bit No. CF H CE H CD H CC H CB H CA H C9 H C8 H C8 H EXF2 RCLK TCLK EXEN2...

  • Page 72: Auto-Reload (Up Or Down Counter)

    On-Chip Peripheral Components C513AO Special Function Register T2MOD (Address C9 H ) Reset Value: XXXX XXX0 B Bit No. C9 H – – – – – – – DCEN T2MOD Function – Not implemented, reserved for future use. DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.
  • Page 73 On-Chip Peripheral Components C513AO C/T2 = 0 Control ÷ 12 P1.0/T2 C/T2 = 1 Overflow < RC2H RC2L < Timer Transition Interrupt Detection Control P1.1/ EXF2 T2EX MCS02584 EXEN2 Figure 6-16 Timer 2 Auto-Reload Mode (DCEN = 0) If EXEN2 = 0, Timer 2 counts up to FFFF H and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RC2H and RC2L.
  • Page 74 On-Chip Peripheral Components C513AO (down counting reload value) Toggle EXF2 Overflow C/T2 = 0 Control ÷ 12 Timer 2 Interrupt P1.0/T2 C/T2 = 1 P1.1/T2EX (1 = UP, 0 = DOWN) RC2H RC2L (up counting reload value) MCS02585 Figure 6-17 Timer 2 Auto-Reload Mode (DCEN = 1) A logic “1”...

  • Page 75: Capture Mode

    On-Chip Peripheral Components C513AO 6.2.2.3 Capture Mode In Capture Mode, there are two options selected by bit EXEN2 in SFR T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which sets bit TF2 in SFR T2CON on overflow.

  • Page 76: Serial Interface (Usart)

    On-Chip Peripheral Components C513AO Serial Interface (USART) The serial port is a full duplex port capable of simultaneous transmit and receive functions. It is also receive-buffered; it can commence reception of a second byte before a previously-received byte has been read from the receive register. (However, if the first byte has not been read before reception of the second byte is complete, one of the bytes will be lost).

  • Page 77: Multiprocessor Communications

    On-Chip Peripheral Components C513AO 6.3.1 Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1.
  • Page 78 On-Chip Peripheral Components C513AO Special Function Register SCON (Address 98 H ) Reset Value: 00 H Special Function Register SBUF (Address 99 H ) Reset Value: XX H Bit No. 9F H 9E H 9D H 9C H 9B H...

  • Page 79: Baudrates

    On-Chip Peripheral Components C513AO 6.3.3 Baudrates There are several possibilities for generating the baudrate clock for the serial interface, depending on the mode in which it is operated. To clarify the terminology, something should be said about the differences between “baudrate clock”...
  • Page 80 On-Chip Peripheral Components C513AO SCON.7/ SCON.6 PCON.7 (SM0/ (SMOD) SM1) Mode 1 ÷ 2 Mode 3 Timer 1 Overflow Baudrate Mode 2 Clock Mode 0 ÷ 6 Only one mode can be selected Note: The switch configuration shows the reset state...

  • Page 81: Using Timer 1 To Generate Baudrates

    On-Chip Peripheral Components C513AO 6.3.3.1 Using Timer 1 to Generate Baudrates When Timer 1 is used as the baudrate generator, the baudrates in Modes 1 and 3 are determined by the timer 1 overflow rate and the value of SMOD as follows: /32 ×...

  • Page 82: Using Timer 2 To Generate Baudrates

    On-Chip Peripheral Components C513AO 6.3.3.2 Using Timer 2 to Generate Baudrates Timer 2 is selected as the baudrate generator by setting TCLK and/or RCLK in T2CON. Note that, simultaneously, the baudrates can be different for transmit and receive. Setting RCLK and/or TCLK puts Timer 2 into its Baudrate Generator Mode, as shown in Figure 6-20.

  • Page 83: Details About Mode 0

    On-Chip Peripheral Components C513AO (thus at /12). As a baudrate generator, however, it increments every state time ( /2). In that case, the baudrate is given by the formula /32 × [65536 – (RC2H, RC2L)] Modes 1 and 3 baudrate = where (RC2H, RC2L) is the content of RC2H and RC2L taken as a 16-bit unsigned integer.
  • Page 84 On-Chip Peripheral Components C513AO Internal Bus Write SBUF & P3.0 Alt. SBUF Output Function Zero Detector Start Shift TX Control Baud < Rate Send TX Clock & Clock P3.1 Alt. Output Function Serial < Port Shift Interrupt Clock & Start...
  • Page 85 On-Chip Peripheral Components C513AO Transmit Receive Figure 6-22 Serial Interface, Mode 0, Timing Diagram User’s Manual 6-39 05.99...

  • Page 86: Details About Mode 1

    On-Chip Peripheral Components C513AO 6.3.5 Details about Mode 1 Ten bits are transmitted through TXD or received through RXD: a start bit (0), eight data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. The baudrate is determined either by the Timer 1 overflow rate, the Timer 2 overflow rate, or both (one for transmit and the other for receive).
  • Page 87 On-Chip Peripheral Components C513AO Internal Bus Write SBUF & < SBUF Zero Detector Shift Start Data TX Control Send ÷ 16 TX Clock Baud Serial < Rate Port Interrupt Clock ÷ 16 Sample Load 1-to-0 SBUF Transition Start RX Control...
  • Page 88 On-Chip Peripheral Components C513AO Transmit Receive Figure 6-24 Serial Interface, Mode 1, Timing Diagram User’s Manual 6-42 05.99...

  • Page 89: Details About Modes 2 And 3

    On-Chip Peripheral Components C513AO 6.3.6 Details about Modes 2 and 3 Eleven bits are transmitted through TXD or received through RXD: a start bit (0), eight data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned a value of “0”...
  • Page 90 On-Chip Peripheral Components C513AO Internal Bus Write SBUF & < SBUF Zero Detector Stop Bit Shift Start Data Generation TX Control Send ÷ 16 TX Clock Baud Serial < Rate Port Interrupt Clock ÷ 16 Sample RX Clock Load 1-to-0...
  • Page 91 On-Chip Peripheral Components C513AO Transmit Receive Figure 6-26 Serial Interface, Mode 2 and 3, Timing Diagram User’s Manual 6-45 05.99...

  • Page 92: Ssc Interface

    C513AO SSC Interface The C513AO microcontroller provides a Synchronous Serial Channel (SSC) unit. This interface is compatible with the popular SPI serial bus interface. It can be used for simple I/O expansion via shift registers, for connection with a variety of peripheral components (such as A/D converters, EEPROMs etc.), or interconnection of several microcontrollers in a master/slave structure.

  • Page 93: General Operation Of The Ssc

    On-Chip Peripheral Components C513AO Because the SSC is a synchronous serial interface, a dedicated clock signal sequence must be provided for each transfer. The SSC has implemented a clock control circuit, which can generate the clock via a baudrate generator in Master Mode, or receive the transfer clock in Slave Mode.

  • Page 94: Baudrate Generation (Master Mode Only)

    On-Chip Peripheral Components C513AO When the SSC is enabled for operation in Master Mode, pins P1.3/SRI, P1.4/STO, and P1.2/SCLK will be switched to the SSC control function; P1.4/STO and P1.2/SCLK actively will drive the lines; and P1.5/SLS will remain as a regular I/O pin.

  • Page 95: Master/Slave Mode Selection

    On-Chip Peripheral Components C513AO 6.4.5 Master/Slave Mode Selection Selection of the SSC unit for Master Mode or Slave Mode is dependent on the hardware configuration and must be made before the SSC will be enabled. Normally, a specific device will operate as either master or slave. The SSC has no on-chip support for multi-master configurations (switching between Master and Slave Mode operation).

  • Page 96: Data/Clock Timing Relationships

    On-Chip Peripheral Components C513AO 6.4.6 Data/Clock Timing Relationships The SSC provides four different clocking schemes for clocking the data in and out of the shift register. The clocking scheme is controlled by two bits in SSCCON: clock polarity (idle state of the clock, control register bit CPOL) and clock/data relationship (phase control, control register bit CPHA).

  • Page 97: Slave Mode Operation

    On-Chip Peripheral Components C513AO 6.4.6.2 Slave Mode Operation Figure 6-30 shows the clock-data/control relationship of the SSC in Slave Mode. When SLS is active (low) and CPHA is “1”, the MSB of the data that was written into the shift register will be provided on the transmitter output after the first clock edge, if the transmitter was enabled by setting the TEN bit to 1.

  • Page 98: Register Description

    On-Chip Peripheral Components C513AO 6.4.7 Register Description The SSC interface has six Special function Registers (SFRs) which are listed in Table 6-5. Table 6-5 Special Function Registers of the COMP Unit Symbol Description Address SSCCON SSC Control Register E8 H...
  • Page 99 On-Chip Peripheral Components C513AO Function CPOL Clock Polarity This bit controls the polarity of the shift clock and in conjunction with the CPHA bit which clock edges are used for sample and shift. CPOL = 0: SCLK idle state is low.
  • Page 100 On-Chip Peripheral Components C513AO The SCIEN Register enables or disables interrupt request for the status bits. SCIEN must be written only when the SSC interrupts are disabled in the general Interrupt Enable Register IE (A8 H ) using bit ESSC, otherwise, unexpected interrupt requests may occur.
  • Page 101 After reset, the contents of the shift register and the receive buffer register are undefined. The register SSCMOD is used to enable test modes during factory test. It must not be written or modified during normal operation of the C513AO. Special Function Register SSCMOD (Address EB H ) Reset Value: 00 H Bit No.

  • Page 102: Interrupt System

    C513AO Interrupt System The C513AO provides seven interrupt sources with two priority levels. Five of the interrupts can be generated by the on-chip peripherals (Timer 0, Timer 1, Timer 2, USART, and SSC) and three of the interrupts may be triggered externally (P1.1/T2EX, P3.2/INT0, P3.3/INT1). A non-maskable eighth interrupt is reserved for external wake-up from power-down mode.
  • Page 103 Interrupt System C513AO Figure 7-1 Interrupt Request Sources User’s Manual 05.99...

  • Page 104: Interrupt Structure

    Interrupt System C513AO Interrupt Structure A common mechanism is used to generate the various interrupts, each source having its own request flag(s) located in a Special Function Register (SFR). Examples include TCON, T2CON and, SCON. When the peripheral or external source meets the condition for an interrupt, the dedicated request flag is set, whether an interrupt is enabled or not.

  • Page 105: Interrupt Registers

    Interrupt System C513AO Interrupt Registers 7.2.1 Interrupt Enable Registers Each interrupt vector can be enabled or disabled individually by setting or clearing the corresponding bit in the SFR IE (Interrupt Enable). This register also contains the global disable bit EA, which can be cleared/set to disable/enable all interrupts.

  • Page 106: Interrupt Request Flags

    Interrupt System C513AO 7.2.2 Interrupt Request Flags The request flags for the different interrupt sources are located in several special function registers. This section describes the locations and meanings of these interrupt request flags in detail. External Interrupts 0 and 1 (P3.2/INT0 and P3.3/INT1) each can be either level-activated or negative transition-activated, depending on bits IT0 and IT1 in SFR TCON.
  • Page 107 Interrupt System C513AO Special Function Register TCON (Address 88 H ) Reset Value: 00 H Bit No. 88 H TCON The shaded bits are not used for interrupt request control. Function Timer 1 overflow flag Set by hardware on Timer/Counter 1 overflow. Cleared by hardware when the processor vectors to the interrupt routine.
  • Page 108 Interrupt System C513AO Interrupt of the serial interface is generated by the request flags RI and TI in SFR SCON. The two request flags of the serial interface are logically OR-ed together. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine of each...
  • Page 109 Interrupt System C513AO Timer 2 interrupt is generated by the logical OR of bit TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may need to determine whether it was TF2 or EXF2 which generated the interrupt, and the bit will need to be cleared by software.
  • Page 110 Interrupt System C513AO SSC Interrupt is generated by a logical OR of flag WCOL and TC in SFR SCF. Both bits can be cleared by software when a “0” is written to the bit location. WCOL is reset by hardware when the SSC transmit data register STB is written with data after a proceeding read operation of the SCF register.

  • Page 111: Interrupt Priority Registers

    Interrupt System C513AO 7.2.3 Interrupt Priority Registers Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in the SFR IP (Interrupt Priority: 0 = low priority, 1 = high priority).
  • Page 112 Interrupt System C513AO If two interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level there is a second priority structure determined by the polling sequence as shown in Table 7-2.

  • Page 113: Interrupt Handling

    Interrupt System C513AO Interrupt Handling The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the proceeding...

  • Page 114: External Interrupts

    Interrupt System C513AO Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in Figure 7-2 then, in accordance with the rules described above, it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed.

  • Page 115: Interrupt Response Time

    Interrupt System C513AO a) Level-Activated Interrupt P3.x/INTx Low-Level Threshold > 1 Machine Cycle b) Transition-Activated Interrupt High-Level Threshold e.g. P3.x/INTx Low-Level Threshold > 1 Machine Cycle > 1 Machine Cycle MCD01860 Transition to be detected Figure 7-3 External Interrupt Detection...

  • Page 116: Fail Safe Mechanisms

    It also times out if a software error is based on a hardware-related problem. The Watchdog Timer in the C513AO is a 15-bit timer which is incremented by a count rate of either /2 or /32 ( /12).
  • Page 117 Fail Safe Mechanisms C513AO Special Function Register WDTREL (Address 86 H ) Reset Value: 00 H Bit No. 86 H Reload Value WDTREL PSEL Function WDTPSEL Watchdog Timer Prescaler Select Bit. When set, the Watchdog Timer is clocked through an additional divide-by-16 prescaler.
  • Page 118 Fail Safe Mechanisms C513AO Immediately after start, the Watchdog Timer is initialized to the reload value programmed to WDTREL.0-WDTREL.6. Register WDTREL is cleared to 00 H after an external hardware reset, an Oscillator Watchdog power on reset, or a Watchdog Timer reset. The lower seven bits of WDTREL can be loaded by software at any time.

  • Page 119: Refreshing The Watchdog Timer

    Fail Safe Mechanisms C513AO 8.1.1 Refreshing the Watchdog Timer At the same time the Watchdog Timer is started, the 7-bit register WDTH is preset by the contents of WDTREL.0 to WDTREL.6. Once started, the Watchdog Timer cannot be stopped by software.

  • Page 120: Oscillator Watchdog Unit

    Fail Safe Mechanisms C513AO Oscillator Watchdog Unit The Oscillator Watchdog (OWD) unit is used for three functions: – Monitoring the on-chip oscillator’s function The watchdog supervises the on-chip oscillator’s frequency. If the frequency is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset.

  • Page 121: Detailed Description Of The Oscillator Watchdog Unit

    Fail Safe Mechanisms C513AO 8.2.1 Detailed Description of the Oscillator Watchdog Unit Figure 8-2 shows the block diagram of the Oscillator Watchdog unit. It consists of an internal RC oscillator which provides the reference frequency for comparison with the frequency of the on-chip oscillator.

  • Page 122: Fast Internal Reset After Power-On

    (instead of an internal reset). 8.2.2 Fast Internal Reset after Power-On The C513AO can use the Oscillator Watchdog for a fast internal reset procedure after power-on. Normally, members of the 8051 family (for example, SAB 80C52) enter their default reset state not before the on-chip oscillator starts.

  • Page 123: Power Saving Modes

    Power Saving Modes C513AO Power Saving Modes The C513AO microcontroller provides three basic power-saving modes: Idle Mode, Slow-down Mode, and Power-down Mode. The functions of the power-saving modes are controlled by bits located in the Special Function Register PCON. PCON is located at SFR address 87 H . PCON1 is located in the mapped SFR area at address 88 and is accessed with RMAP = 1.
  • Page 124 Power Saving Modes C513AO Special Function Register PCON1 (Mapped Address 88 H) Reset Value: 0XXXXXXX B Bit No. 88 H EWPD – – – – – – – PCON1 Symbol Function – Reserved for future use. EWPD External Wake-up From Power-down Enable Bit Setting EWPD before entering Power-down Mode enables external wake-up from Power-down Mode capability via the pin INT0.

  • Page 125: Idle Mode

    C513AO Idle Mode In Idle Mode, the oscillator of the C513AO continues to run; but, the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the Synchronous Serial Channel (SSC) interface, and all timers are still provided with the clock. CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during Idle Mode.
  • Page 126 Power Saving Modes C513AO As in Normal Operation Mode, the ports can be used as inputs during Idle Mode. Thus, a capture or reload operation can be triggered, the timers can be used to count external events, and external interrupts will be detected.

  • Page 127: Slow-Down Mode Operation

    (for example, if the controller is waiting for an input signal). As a CMOS device, the C513AO has an almost linear dependence of the operating frequency and the power supply current, so that a reduction of the operating frequency results in reduced power consumption.

  • Page 128: Power-Down Mode

    Power Saving Modes C513AO Power-down Mode In Power-down Mode, the on-chip oscillator which operates with the XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM, and the SFRs are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFRs.

  • Page 129: Exit From Power-Down Mode

    Power Saving Modes C513AO 9.3.2 Exit from Power-down Mode The C513AO can recover from Power-down Mode in one of the following ways: – Hardware reset – Wake-up from power-down through pin P3.2/INT0 If the bit EWPD in SFR PCON is “0” during power-down entry, the only way to exit from Power-down Mode is a hardware reset.
  • Page 130 Figure 9-1 Wake-up from Power-Down Mode Procedure All interrupts of the C513AO are disabled from Phase 2 until the end of Phase 4. Other interrupts can be handled after the RETI instruction of the wake-up interrupt routine. Note: To avoid any unintentional external interrupt request, the user should ensure that P3.2/INT0 is set back to high level after a wake-up request, prior to completion of the wake-up sequence.

  • Page 131: Otp Memory Operation

    Further, the inputs PMSEL1,0 are required in Programming Mode to select the access types (such as program/verify data, write lock bits, etc.). In Programming Mode, and a clock signal at the XTAL pins must be applied to the C513AO-2E. The 11.5 V external programming voltage is input through the EA/ pin.

  • Page 132: Pin Configuration

    OTP Memory Operation C513AO-2E Only 10.2 Pin Configuration Figure 10-2 to Figure 10-4 show the detailed pin configurations of the C513AO-2E in different packages in Programming Mode. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. RESET PMSEL0 C513AO-2E PMSEL1 PROG...
  • Page 133 OTP Memory Operation C513AO-2E Only 28 27 26 25 24 23 22 21 20 19 18 A5/A13 N.C. PALE PSEN PSEL PROG PMSEL1 C513AO-2E N.C. N.C. PMSEL0 RESET N.C. N.C. N.C. 40 41 42 43 44 1 2 3 4 5 6...
  • Page 134 OTP Memory Operation C513AO-2E Only 32 31 30 29 28 27 26 25 24 23 A4/A12 A3/A11 A2/A10 A1/A9 A0/A8 C513AO-2E N.C. N.C. XTAL1 N.C. XTAL2 N.C. N.C. N.C. N.C. 9 10 11 MCP04021 Figure 10-4 OTP Programming Mode Pin Configuration: P-MQFP-44 (top view) User’s Manual...

  • Page 135: Otp Programming Mode - Pin Definitions

    OTP Memory Operation C513AO-2E Only 10.3 OTP Programming Mode - Pin Definitions The functional description of all C513AO-2E pins which are required for OTP memory programming are provided in Table 10-1. Table 10-1 Pin Definitions and Functions of the C513AO-2E in Programming Mode...
  • Page 136 OTP Memory Operation C513AO-2E Only Table 10-1 Pin Definitions and Functions of the C513AO-2E in Programming Mode (cont’d) Symbol Pin Number Function XTAL2 XTAL2 Output of the inverting oscillator amplifier. – Ground – – Ground, Optional – Power Supply (+ 5 V) –...

  • Page 137: Otp Programming Mode Selection

    OTP Memory Operation C513AO-2E Only 10.4 OTP Programming Mode Selection Selection of OTP Programming Mode consists of two aspects: • Basic Programming Mode selection • Access Mode selection Basic Programming Mode selection enables access of the device’s OTP memory through the programming interface logic.

  • Page 138: Otp Memory Access Mode Selection

    Programming Mode. 10.4.2 OTP Memory Access Mode Selection When the C513AO-2E has been put into Programming Mode using basic programming mode selection, several Access Modes of the OTP memory programming interface are available. The conditions for the different control signals of these access modes are listed in Table 10-2.

  • Page 139: Program/Read Otp Memory Bytes

    OTP Memory Operation C513AO-2E Only 10.5 Program/Read OTP Memory Bytes The Program/Read OTP Memory Byte Access Mode is defined by PMSEL1,0 = 1,1. It is initiated when the PMSEL1,0 = 1,1 is valid at the rising edge of PALE. With the falling edge of PALE, the upper addresses A8-A13 of the 14-bit OTP memory address are latched.
  • Page 140 OTP Memory Operation C513AO-2E Only Figure 10-7 shows a waveform example of the Program/Read Access Mode for several OTP memory bytes. In this example, OTP memory locations 3FD H to 400 H are programmed. Thereafter, OTP memory locations 400 H and 3FD H are read.

  • Page 141: Lock Bits Programming / Read

    ROM boundary), is still possible. Note: A “1” means that the lock bit is not programmed. A “0” means that lock bit is programmed. For an OTP verify operation at Protection Level 1, the C513AO-2E must be put into the OTP Verification Mode.
  • Page 142 OTP Memory Operation C513AO-2E Only Figure 10-8 shows the waveform of a lock bit write/read access. To simplify the illustration, the PROG pulse has been shortened. In reality, for Lock Bit programming, a 100 µs PROG low pulse must be applied.

  • Page 143: Access Of Version Bytes

    10.7 Access of Version Bytes The C513AO-2E provides three version bytes at address locations FC H , FD H , and FE H . The information stored in the version bytes is defined by the mask of each microcontroller step, Therefore, the version bytes can be read, but not written.
  • Page 144 Index C513AO Index ALE signal ..... .4-4 ALE switch-off control ... . .4-4 Overlapping of data/program memory 4-3 Program memory access .
  • Page 145 Index C513AO IT0 ......3-8 PCON14 ......3-7 IT1 .
  • Page 146 Index C513AO Unprotected ROM mode ..4-6 T2 ......3-8 Unprotected ROM verifiy timimg .
  • Page 147 Index C513AO Reset operation ....8-4 Starting of the WDT ....8-3 Time-out periods .

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