Infineon AIROC CYW43012 Manual page 27

Low-power system design with AIROC™ Wi-Fi & Bluetooth® combo
chip and PSoC™ 6 MCU
PSoC™ 6 MCU power optimization techniques
Do the following to disable an unused SRAM block in the code:
Find out the SRAM consumed by the application. CPU Stack statistics and other memory analyzer tools
1.
supported in the platforms can be used to determine memory usage.
2. Update the linker script to reduce the RAM size to the value calculated above. Make it a multiple of 32 KB
and fit the size calculated in Step 1. This step is compiler-dependent as well.
GCC (cy8c6xx*_cm4_dual.ld file):
ram
ARM (cy8c6xx*_cm4_dual.sct file):
#define RAM_SIZE
IAR (cy8c6xx*_cm4_dual.icf file):
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
define symbol __ICFEDIT_region_IRAM1_end__
CLANG (cy8c6xx*_dual.mk file):
export RAM_SIZE_CM4
3. Add code to disable SRAM blocks and/or controllers depending on the device and memory consumed. For
example, consider the following cases:
PSoC™ 6 MCU with 1 MB of SRAM has three controllers – SRAM0 (512 KB), SRAM1 (256 KB), and SRAM2
a)
(256 KB). As an example, if your application requires only 450 KB of SRAM (= 480 KB, multiple of 32 KB), you
can completely disable SRAM1 and SRAM2 controllers and the last block of SRAM0 using the following
code:
CPUSS->RAM0_PWR_MACRO_CTL[15]= 0x05FA0000; //Disable block 15 in SRAM0
CPUSS->RAM1_PWR_CTL= 0x05FA0000;//Disable SRAM1
CPUSS->RAM2_PWR_CTL= 0x05FA0000;//Disable SRAM2
If you want to add system call support in the same application, you should not disable the last block of the
b)
SRAM region, which is the last 32 KB block in SRAM2:
CPUSS->RAM0_PWR_MACRO_CTL[15]= 0x05FA0000;
CPUSS->RAM1_PWR_CTL= 0x05FA0000;
for(int32 i = 0; i < 15; i++) //Do not disable block 15 alone.
CPUSS-> RAM0_PWR_MACRO_CTL[i]= 0x05FA0000;
Application note
(rwx) : ORIGIN = 0x08002000, LENGTH = 0xFD800
0x000FD800
:= 0x000FD800
= 0x080FF7FF;
27 002-27910 Rev. *C
2023-05-29