Chipset Overview - Supermicro X6DVA-4G2 User Manual

Chapter 1: Introduction
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Chipset Overview

Built upon the functionality and the capability of the E7320 chipset, the X6DVA-
4G2/X6DVA-EG2 motherboard provides the performance and feature set required
for dual processor-based servers with confi guration options optimized for commu-
nications, presentation, storage, computation or database applications. The Intel
E7320 chipset consists of the following components: the E7320 Memory Controller
Hub (MCH), the I/O Controller Hub (6300ESB ICH), and the PCI-X Hub (PXH).
The E7320 MCH supports a single or dual 64-bit Xeon processors with Front Side
Bus speeds of up to 800 MHz. Its memory controller provides direct connection
to two channels of registered DDRII 400 with a marched system bus address and
data bandwidths of up to 6.4GB/s. The E7320 also supports the new PCI Express
high speed serial I/O interface for superior I/O bandwidth. The MCH provides
confi gurable x8 PCI Express interfaces which may alternatively be confi gured as
two independent x4 PCI Express interfaces. These interfaces support connection
of the MCH to a variety of other bridges that are compliant with the PCI Express
Interface Specifi cation, Rev. 1.0a. The MCH interfaces with the 6300ESB I/O
Controller Hub (6300ESB ICH) via Hub Interface. The PCI- Bus provides con-
nection between a PCI Express interface and two independent PCI bus interfaces
that can be confi gured for standard PCI 2.3 protocol, as well as the enhanced
high-frequency PCI-X protocol. The PXH can be confi gured to support for 32- or
64-bit PCI devices running at 33 MHz, 66 MHz, 100 MHz, and 133 MHz.
6300ESB ICH System Features
In addition to providing the I/O subsystem with access to the rest of the system, the
6300ESB I/O Controller Hub (6300ESB ICH) integrates many I/O functions.
The 6300ESB integrates: 2-channel Ultra ATA/100 Bus Master IDE Controller,
two Serial ATA (SATA) Host Controllers, SMBus 2.0 Controller, LPC/Flash BIOS
Interface, PCI-X (66MHz) 1.0 Interface, PCI 2.2 Interface and System Manage-
ment Controller.
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