基本ブロック - IAI GO-5000M-PGE User Manual

6.2.8.1
基本ブロック
Soft Trigger
LVAL IN
FVAL IN
Exposure Active
Frame Trigger Wait
Frame Active
User out 0
User out 1
Action 1
Action 2
GPIO 5 (OPT IN)
Pixel Clock
GO-5000M-PGE / GO-5000C-PGE
Sel Bit (5,0)
NAND 1
NAND 2
Cross Point
Switch
12 bit Counter
図 6． GPIO 接続信号図
- 17 -
Sel Bit (7)
InvEn
Sel Bit (7)
InvEn
InvEN
NAND
Sel Bit (7)
InvEN
Pulse Generator 0
20 bit counter x 1
Trigger 0 (Acquisition Start)
Trigger 1 (Acquisition Stop)
Trigger 2 (Frame Start)
Trigger 3 (Transfer Start)
GPIO 1 (OPT OUT 1)
GPIO 2 (OPT OUT 2)
Time Stamp Reset
Pulse Generator
CLR